mesa/src/gallium/drivers
Charmaine Lee b4c4ee0762 svga: disable rasterization if rasterizer_discard is set or FS undefined
With this patch, rasterization will be disabled if the
rasterizer_discard flag is set or the fragment shader
is undefined due to missing position output from the
vertex/geometry shader.

Tested with piglit test glsl-1.50-geometry-primitive-id-restart.
Also tested with full MTT glretrace and piglit.

v2: As suggested by Roland, to properly disable rasterization, besides
    setting FS to NULL, we will also need to disable depth and stencil test.

v3: As suggested by Brian, set SVGA_NEW_DEPTH_STENCIL_ALPHA dirty bit
    in svga_bind_rasterizer_state() if the rasterizer_discard flag is
    changed.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-07 13:46:43 -06:00
..
ddebug ddebug: add resource_commit pass-through 2017-04-05 10:37:16 +02:00
etnaviv Revert "etnaviv: Cannot render to rb-swapped formats" 2017-04-05 19:58:25 +02:00
freedreno gallium: add PIPE_CAP_TGSI_BALLOT 2017-04-05 15:29:31 +02:00
i915 gallium: add PIPE_CAP_TGSI_BALLOT 2017-04-05 15:29:31 +02:00
imx imx: gallium driver for imx-drm scanout driver 2017-01-12 19:27:11 +00:00
llvmpipe gallium: add PIPE_CAP_TGSI_BALLOT 2017-04-05 15:29:31 +02:00
noop gallium: s/uint/enum pipe_shader_type/ for set_constant_buffer() 2017-03-08 08:50:20 -07:00
nouveau gallium: add PIPE_CAP_TGSI_BALLOT 2017-04-05 15:29:31 +02:00
r300 gallium: add PIPE_CAP_TGSI_BALLOT 2017-04-05 15:29:31 +02:00
r600 gallium: add PIPE_CAP_TGSI_BALLOT 2017-04-05 15:29:31 +02:00
radeon gallium/radeon: fix typo in radeon_winsys.h 2017-04-07 00:48:19 +02:00
radeonsi radeonsi: enable ARB_shader_ballot 2017-04-05 15:29:44 +02:00
rbug gallium: decrease the size of pipe_resource - 64 -> 48 bytes 2017-04-04 11:14:43 +02:00
softpipe gallium: add PIPE_CAP_TGSI_BALLOT 2017-04-05 15:29:31 +02:00
svga svga: disable rasterization if rasterizer_discard is set or FS undefined 2017-04-07 13:46:43 -06:00
swr swr: [rasterizer core] SIMD16 Frontend WIP 2017-04-05 18:20:45 -05:00
trace trace: add resource_commit pass-through 2017-04-05 10:37:16 +02:00
vc4 gallium: add PIPE_CAP_TGSI_BALLOT 2017-04-05 15:29:31 +02:00
virgl gallium: add PIPE_CAP_TGSI_BALLOT 2017-04-05 15:29:31 +02:00