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7a89a0d9ed
On Broadwell and above, we have to use different MOCS settings to allow the kernel to take over and disable caching when needed for external buffers. On Broadwell, this is especially important because the kernel can't disable eLLC so we have to do it in userspace. We very badly don't want to do that on everything so we need separate MOCS for external and internal BOs. In order to do this, we add an anv-specific BO flag for "external" and use that to distinguish between buffers which may be shared with other processes and/or display and those which are entirely internal. That, together with an anv_mocs_for_bo helper lets us choose the right MOCS settings for each BO use. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99507 Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
305 lines
12 KiB
C
305 lines
12 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "vk_format_info.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#if GEN_GEN == 7 && !GEN_IS_HASWELL
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static int64_t
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clamp_int64(int64_t x, int64_t min, int64_t max)
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{
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if (x < min)
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return min;
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else if (x < max)
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return x;
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else
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return max;
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}
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void
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gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
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uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count;
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const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors;
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struct anv_state scissor_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
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for (uint32_t i = 0; i < count; i++) {
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const VkRect2D *s = &scissors[i];
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/* Since xmax and ymax are inclusive, we have to have xmax < xmin or
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* ymax < ymin for empty clips. In case clip x, y, width height are all
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* 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
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* what we want. Just special case empty clips and produce a canonical
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* empty clip. */
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static const struct GEN7_SCISSOR_RECT empty_scissor = {
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.ScissorRectangleYMin = 1,
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.ScissorRectangleXMin = 1,
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.ScissorRectangleYMax = 0,
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.ScissorRectangleXMax = 0
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};
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const int max = 0xffff;
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struct GEN7_SCISSOR_RECT scissor = {
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/* Do this math using int64_t so overflow gets clamped correctly. */
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.ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
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.ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
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.ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, fb->height - 1),
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.ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, fb->width - 1)
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};
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if (s->extent.width <= 0 || s->extent.height <= 0) {
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GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
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&empty_scissor);
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} else {
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GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
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}
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}
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anv_batch_emit(&cmd_buffer->batch,
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GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
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ssp.ScissorRectPointer = scissor_state.offset;
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}
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anv_state_flush(cmd_buffer->device, scissor_state);
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}
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#endif
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static const uint32_t vk_to_gen_index_type[] = {
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[VK_INDEX_TYPE_UINT16] = INDEX_WORD,
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[VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
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};
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static const uint32_t restart_index_for_type[] = {
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[VK_INDEX_TYPE_UINT16] = UINT16_MAX,
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[VK_INDEX_TYPE_UINT32] = UINT32_MAX,
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};
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void genX(CmdBindIndexBuffer)(
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VkCommandBuffer commandBuffer,
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VkBuffer _buffer,
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VkDeviceSize offset,
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VkIndexType indexType)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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if (GEN_IS_HASWELL)
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cmd_buffer->state.restart_index = restart_index_for_type[indexType];
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cmd_buffer->state.gfx.gen7.index_buffer = buffer;
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cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type[indexType];
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cmd_buffer->state.gfx.gen7.index_offset = offset;
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}
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static uint32_t
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get_depth_format(struct anv_cmd_buffer *cmd_buffer)
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{
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const struct anv_render_pass *pass = cmd_buffer->state.pass;
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const struct anv_subpass *subpass = cmd_buffer->state.subpass;
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if (!subpass->depth_stencil_attachment)
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return D16_UNORM;
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struct anv_render_pass_attachment *att =
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&pass->attachments[subpass->depth_stencil_attachment->attachment];
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switch (att->format) {
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case VK_FORMAT_D16_UNORM:
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case VK_FORMAT_D16_UNORM_S8_UINT:
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return D16_UNORM;
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case VK_FORMAT_X8_D24_UNORM_PACK32:
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case VK_FORMAT_D24_UNORM_S8_UINT:
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return D24_UNORM_X8_UINT;
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case VK_FORMAT_D32_SFLOAT:
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case VK_FORMAT_D32_SFLOAT_S8_UINT:
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return D32_FLOAT;
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default:
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return D16_UNORM;
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}
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}
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void
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genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
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struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
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uint32_t sf_dw[GENX(3DSTATE_SF_length)];
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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.DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
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.LineWidth = d->line_width,
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.GlobalDepthOffsetConstant = d->depth_bias.bias,
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.GlobalDepthOffsetScale = d->depth_bias.slope,
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.GlobalDepthOffsetClamp = d->depth_bias.clamp
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};
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GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
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}
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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GENX(COLOR_CALC_STATE_length) * 4,
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64);
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struct GENX(COLOR_CALC_STATE) cc = {
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.BlendConstantColorRed = d->blend_constants[0],
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.BlendConstantColorGreen = d->blend_constants[1],
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.BlendConstantColorBlue = d->blend_constants[2],
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.BlendConstantColorAlpha = d->blend_constants[3],
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.StencilReferenceValue = d->stencil_reference.front & 0xff,
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.BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
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};
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GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
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anv_state_flush(cmd_buffer->device, cc_state);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
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ccp.ColorCalcStatePointer = cc_state.offset;
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}
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}
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
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uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
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struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
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.StencilTestMask = d->stencil_compare_mask.front & 0xff,
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.StencilWriteMask = d->stencil_write_mask.front & 0xff,
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.BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
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.BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
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.StencilBufferWriteEnable =
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(d->stencil_write_mask.front || d->stencil_write_mask.back) &&
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pipeline->writes_stencil,
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};
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GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
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struct anv_state ds_state =
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anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
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pipeline->gen7.depth_stencil_state,
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GENX(DEPTH_STENCIL_STATE_length), 64);
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anv_batch_emit(&cmd_buffer->batch,
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GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
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dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
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}
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}
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if (cmd_buffer->state.gfx.gen7.index_buffer &&
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cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER)) {
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struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer;
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uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
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#if GEN_IS_HASWELL
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anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
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vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
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vf.CutIndex = cmd_buffer->state.restart_index;
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}
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#endif
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
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#if !GEN_IS_HASWELL
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ib.CutIndexEnable = pipeline->primitive_restart;
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#endif
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ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type;
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ib.IndexBufferMOCS = anv_mocs_for_bo(cmd_buffer->device,
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buffer->address.bo);
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ib.BufferStartingAddress = anv_address_add(buffer->address,
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offset);
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ib.BufferEndingAddress = anv_address_add(buffer->address,
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buffer->size);
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}
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}
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cmd_buffer->state.gfx.dirty = 0;
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}
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void
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genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
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bool enable)
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{
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/* The NP PMA fix doesn't exist on gen7 */
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}
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void genX(CmdSetEvent)(
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VkCommandBuffer commandBuffer,
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VkEvent event,
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VkPipelineStageFlags stageMask)
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{
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anv_finishme("Implement events on gen7");
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}
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void genX(CmdResetEvent)(
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VkCommandBuffer commandBuffer,
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VkEvent event,
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VkPipelineStageFlags stageMask)
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{
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anv_finishme("Implement events on gen7");
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}
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void genX(CmdWaitEvents)(
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VkCommandBuffer commandBuffer,
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uint32_t eventCount,
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const VkEvent* pEvents,
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VkPipelineStageFlags srcStageMask,
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VkPipelineStageFlags destStageMask,
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uint32_t memoryBarrierCount,
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const VkMemoryBarrier* pMemoryBarriers,
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uint32_t bufferMemoryBarrierCount,
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const VkBufferMemoryBarrier* pBufferMemoryBarriers,
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uint32_t imageMemoryBarrierCount,
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const VkImageMemoryBarrier* pImageMemoryBarriers)
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{
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anv_finishme("Implement events on gen7");
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genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
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false, /* byRegion */
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memoryBarrierCount, pMemoryBarriers,
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bufferMemoryBarrierCount, pBufferMemoryBarriers,
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imageMemoryBarrierCount, pImageMemoryBarriers);
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}
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