Timur Kristóf b3c6b48493 ac/nir/tess: Use LDS IO mapping when loading tess levels from LDS. ... By accident, the VRAM mapping was used. This doesn't cause issues in practice because the offsets are really the same, but it's still better to fix this. Fixes: c61eb54806 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28739>		2024-04-19 08:54:24 +00:00
..
addrlib	amd: fix addrlib regression	2024-03-22 08:25:21 +00:00
ci	radV/ci: reduce the parallelism of navi21 to 3	2024-04-18 09:24:22 +00:00
common	ac/nir/tess: Use LDS IO mapping when loading tess levels from LDS.	2024-04-19 08:54:24 +00:00
compiler	radv: Run DCE before deleting I/O variables.	2024-04-18 18:35:07 +00:00
drm-shim	amd: Use align64 instead of ALIGN for 64 bit value parameter	2024-01-03 22:02:17 +00:00
llvm	nir: add nir_intrinsic_optimization_barrier_sgpr_amd	2024-04-13 16:45:08 +00:00
registers	amd/registers: add correct gfx11.x enums for BINNING_MODE	2024-03-11 23:36:55 +00:00
vpelib	radeonsi/vpe: support vpe 1.1	2024-03-25 00:59:02 +00:00
vulkan	radv: Calculate VRAM tess patch size independently of LDS size.	2024-04-19 08:54:23 +00:00
meson.build	amd,radeonsi: add libvpe	2023-12-01 00:23:38 +00:00