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b1b581f855
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35352>
464 lines
17 KiB
C
464 lines
17 KiB
C
/*
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* Copyright © 2021 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef AC_NIR_H
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#define AC_NIR_H
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#include "ac_hw_stage.h"
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#include "ac_shader_args.h"
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#include "ac_shader_util.h"
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#include "nir_defines.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum
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{
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/* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */
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AC_EXP_PARAM_OFFSET_0 = 0,
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AC_EXP_PARAM_OFFSET_31 = 31,
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/* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */
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AC_EXP_PARAM_DEFAULT_VAL_0000 = 64,
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AC_EXP_PARAM_DEFAULT_VAL_0001,
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AC_EXP_PARAM_DEFAULT_VAL_1110,
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AC_EXP_PARAM_DEFAULT_VAL_1111,
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AC_EXP_PARAM_UNDEFINED = 255,
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};
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enum {
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AC_EXP_FLAG_COMPRESSED = (1 << 0),
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AC_EXP_FLAG_DONE = (1 << 1),
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AC_EXP_FLAG_VALID_MASK = (1 << 2),
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};
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struct ac_nir_config {
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enum amd_gfx_level gfx_level;
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bool uses_aco;
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};
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/* Maps I/O semantics to the actual location used by the lowering pass. */
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typedef unsigned (*ac_nir_map_io_driver_location)(unsigned semantic);
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/* Forward declaration of nir_builder so we don't have to include nir_builder.h here */
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struct nir_builder;
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typedef struct nir_builder nir_builder;
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struct nir_xfb_info;
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typedef struct nir_xfb_info nir_xfb_info;
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/* Executed by ac_nir_cull when the current primitive is accepted. */
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typedef void (*ac_nir_cull_accepted)(nir_builder *b, void *state);
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void
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ac_nir_set_options(struct radeon_info *info, bool use_llvm,
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nir_shader_compiler_options *options);
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nir_def *
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ac_nir_load_arg_at_offset(nir_builder *b, const struct ac_shader_args *ac_args,
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struct ac_arg arg, unsigned relative_index);
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nir_def *
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ac_nir_load_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_arg arg);
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nir_def *
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ac_nir_load_arg_upper_bound(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_arg arg,
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unsigned upper_bound);
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void ac_nir_store_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_arg arg,
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nir_def *val);
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nir_def *
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ac_nir_unpack_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_arg arg,
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unsigned rshift, unsigned bitwidth);
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bool ac_nir_lower_sin_cos(nir_shader *shader);
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bool ac_nir_lower_intrinsics_to_args(nir_shader *shader, const enum amd_gfx_level gfx_level,
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bool has_ls_vgpr_init_bug, const enum ac_hw_stage hw_stage,
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unsigned wave_size, unsigned workgroup_size,
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const struct ac_shader_args *ac_args);
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nir_xfb_info *ac_nir_get_sorted_xfb_info(const nir_shader *nir);
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bool ac_nir_optimize_outputs(nir_shader *nir, bool sprite_tex_disallowed,
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int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS],
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uint8_t param_export_index[NUM_TOTAL_VARYING_SLOTS]);
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typedef struct {
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/* Per-vertex slots and tess levels. */
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uint64_t vram_output_mask;
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uint64_t lds_output_mask;
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uint64_t vgpr_output_mask; /* Hold the output values in VGPRs until the end. */
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/* Generic per-patch slots. */
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uint32_t vram_patch_output_mask;
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uint32_t lds_patch_output_mask;
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uint32_t vgpr_patch_output_mask; /* Hold the output values in VGPRs until the end. */
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/* The highest index returned by map_io + 1. */
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uint8_t highest_remapped_vram_output;
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uint8_t highest_remapped_vram_patch_output;
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} ac_nir_tess_io_info;
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void
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ac_nir_get_tess_io_info(const nir_shader *tcs, const nir_tcs_info *tcs_info, uint64_t tes_inputs_read,
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uint32_t tes_patch_inputs_read, ac_nir_map_io_driver_location map_io,
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bool remapped_outputs_include_tess_levels, ac_nir_tess_io_info *io_info);
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bool
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ac_nir_lower_ls_outputs_to_mem(nir_shader *ls,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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bool tcs_in_out_eq,
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uint64_t tcs_inputs_via_temp,
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uint64_t tcs_inputs_via_lds);
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bool
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ac_nir_lower_hs_inputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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bool tcs_in_out_eq,
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uint64_t tcs_inputs_via_temp,
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uint64_t tcs_inputs_via_lds);
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bool
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ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, const nir_tcs_info *info,
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const ac_nir_tess_io_info *io_info,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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unsigned wave_size);
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bool
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ac_nir_lower_tes_inputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map);
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void
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ac_nir_compute_tess_wg_info(const struct radeon_info *info, const ac_nir_tess_io_info *io_info,
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unsigned tcs_vertices_out, unsigned wave_size, bool tess_uses_primid,
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unsigned num_tcs_input_cp, unsigned lds_input_vertex_size,
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unsigned num_remapped_tess_level_outputs, unsigned *num_patches_per_wg,
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unsigned *hw_lds_size);
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bool
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ac_nir_lower_es_outputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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unsigned esgs_itemsize,
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uint64_t gs_inputs_read);
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bool
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ac_nir_lower_gs_inputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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bool triangle_strip_adjacency_fix);
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bool
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ac_nir_lower_indirect_derefs(nir_shader *shader,
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enum amd_gfx_level gfx_level);
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typedef struct {
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const struct radeon_info *hw_info;
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unsigned max_workgroup_size;
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unsigned wave_size;
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/* The mask of clip and cull distances that the shader should export. */
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uint8_t export_clipdist_mask;
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/* The mask of clip and cull distances that the shader should cull against.
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* If no clip and cull distance outputs are present, it will load clip planes and cull
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* either against CLIP_VERTEX or POS.
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*/
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uint8_t cull_clipdist_mask;
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/* This skips exporting cull distances to increase throughput by reducing the number of pos exports.
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* If this is set, cull_clipdist_mask must be set to cull against cull distances in the shader because
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* the hw won't do it without the exports. The best case scenario is 100% increase in throughput
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* (2 pos exports -> 1 pos export).
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*/
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bool dont_export_cull_distances;
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bool write_pos_to_clipvertex;
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/* Remove clip/cull distance components that are missing in export_clipdist_mask, improving
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* throughput by up to 50% (3 pos exports -> 2 pos exports). The caller shouldn't set no-op
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* components (>= 0) in export_clipdist_mask to remove those completely. No-op components
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* should be determined by nir_opt_clip_cull_const before this.
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*/
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bool pack_clip_cull_distances;
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const uint8_t *vs_output_param_offset; /* GFX11+ */
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bool has_param_exports;
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bool can_cull;
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bool disable_streamout;
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bool has_gen_prim_query;
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bool has_xfb_prim_query;
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bool use_gfx12_xfb_intrinsic;
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bool has_gs_invocations_query;
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bool has_gs_primitives_query;
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bool kill_pointsize;
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bool kill_layer;
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bool force_vrs;
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bool compact_primitives;
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/* Skip culling dependent on the viewport state, which is frustum culling and small prim
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* culling. Set this when the shader writes the viewport index.
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*/
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bool skip_viewport_state_culling;
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/* Use the point-triangle intersection to cull small triangles. */
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bool use_point_tri_intersection;
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/* VS */
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unsigned num_vertices_per_primitive;
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bool early_prim_export;
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bool passthrough;
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bool use_edgeflags;
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bool export_primitive_id;
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bool export_primitive_id_per_prim;
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uint32_t instance_rate_inputs;
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} ac_nir_lower_ngg_options;
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bool
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ac_nir_lower_ngg_nogs(nir_shader *shader, const ac_nir_lower_ngg_options *options,
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uint32_t *out_lds_vertex_size);
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bool
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ac_nir_lower_ngg_gs(nir_shader *shader, const ac_nir_lower_ngg_options *options,
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uint32_t *out_lds_vertex_size);
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bool
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ac_nir_lower_ngg_mesh(nir_shader *shader,
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const struct radeon_info *hw_info,
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uint32_t clipdist_enable_mask,
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const uint8_t *vs_output_param_offset,
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bool has_param_exports,
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bool *out_needs_scratch_ring,
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unsigned wave_size,
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unsigned workgroup_size,
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bool multiview,
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bool has_query,
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bool fast_launch_2);
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bool
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ac_nir_lower_task_outputs_to_mem(nir_shader *shader,
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unsigned task_payload_entry_bytes,
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unsigned task_num_entries,
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bool has_query);
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bool
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ac_nir_lower_mesh_inputs_to_mem(nir_shader *shader,
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unsigned task_payload_entry_bytes,
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unsigned task_num_entries);
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bool
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ac_nir_lower_global_access(nir_shader *shader);
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bool ac_nir_lower_resinfo(nir_shader *nir, enum amd_gfx_level gfx_level);
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bool ac_nir_lower_image_opcodes(nir_shader *nir);
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typedef struct ac_nir_gs_output_info {
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const uint8_t *streams;
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const uint8_t *streams_16bit_lo;
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const uint8_t *streams_16bit_hi;
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const uint8_t *varying_mask;
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const uint8_t *varying_mask_16bit_lo;
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const uint8_t *varying_mask_16bit_hi;
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const uint8_t *sysval_mask;
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/* type for each 16bit slot component */
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nir_alu_type (*types_16bit_lo)[4];
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nir_alu_type (*types_16bit_hi)[4];
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} ac_nir_gs_output_info;
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nir_shader *
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ac_nir_create_gs_copy_shader(const nir_shader *gs_nir,
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enum amd_gfx_level gfx_level,
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uint32_t export_clipdist_mask,
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bool write_pos_to_clipvertex,
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bool pack_clip_cull_distances,
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const uint8_t *param_offsets,
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bool has_param_exports,
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bool disable_streamout,
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bool kill_pointsize,
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bool kill_layer,
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bool force_vrs,
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ac_nir_gs_output_info *output_info);
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bool
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ac_nir_lower_legacy_vs(nir_shader *nir,
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enum amd_gfx_level gfx_level,
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uint32_t export_clipdist_mask,
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bool write_pos_to_clipvertex,
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bool pack_clip_cull_distances,
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const uint8_t *param_offsets,
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bool has_param_exports,
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bool export_primitive_id,
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bool disable_streamout,
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bool kill_pointsize,
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bool kill_layer,
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bool force_vrs);
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bool
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ac_nir_lower_legacy_gs(nir_shader *nir,
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bool has_gen_prim_query,
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bool has_pipeline_stats_query,
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ac_nir_gs_output_info *output_info);
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/* This is a pre-link pass. It should only eliminate code and do lowering that mostly doesn't
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* generate AMD-specific intrinsics.
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*/
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typedef struct {
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/* System values. */
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bool force_center_interp_no_msaa; /* true if MSAA is disabled, false may mean that the state is unknown */
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bool uses_vrs_coarse_shading;
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bool load_sample_positions_always_loads_current_ones;
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bool dynamic_rasterization_samples;
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int force_front_face; /* 0 -> keep, 1 -> set to true, -1 -> set to false */
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bool optimize_frag_coord; /* TODO: remove this after RADV can handle it */
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bool frag_coord_is_center; /* GL requirement for sample shading */
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/* frag_coord/pixel_coord:
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* allow_pixel_coord && (frag_coord_is_center || ps_iter_samples == 1 ||
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* force_center_interp_no_msaa ||
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* the fractional part of frag_coord.xy isn't used):
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* * frag_coord.xy is replaced by u2f(pixel_coord) + 0.5.
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* else:
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* * pixel_coord is replaced by f2u16(frag_coord.xy)
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* * ps_iter_samples == 0 means the state is unknown.
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*
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* barycentrics:
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* force_center_interp_no_msaa:
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* * All barycentrics including at_sample but excluding at_offset are changed to
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* barycentric_pixel
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* ps_iter_samples >= 2:
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* * All barycentrics are changed to per-sample interpolation except at_offset/at_sample.
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* * barycentric_at_sample(sample_id) is replaced by barycentric_sample.
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*
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* sample_mask_in:
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* force_center_interp_no_msaa && !uses_vrs_coarse_shading:
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* * sample_mask_in is replaced by b2i32(!helper_invocation)
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* ps_iter_samples == 2, 4:
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* * sample_mask_in is changed to (sample_mask_in & (ps_iter_mask << sample_id))
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* ps_iter_samples == 8:
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* * sample_mask_in is replaced by 1 << sample_id.
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*
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* When ps_iter_samples is equal to rasterization samples, set ps_iter_samples = 8 for this pass.
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*/
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unsigned ps_iter_samples;
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/* fbfetch_output */
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bool fbfetch_is_1D;
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bool fbfetch_layered;
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bool fbfetch_msaa;
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bool fbfetch_apply_fmask;
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/* Outputs. */
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bool clamp_color; /* GL only */
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bool alpha_test_alpha_to_one; /* GL only, this only affects alpha test */
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enum compare_func alpha_func; /* GL only */
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bool keep_alpha_for_mrtz; /* this prevents killing alpha based on spi_shader_col_format_hint */
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unsigned spi_shader_col_format_hint; /* this only shrinks and eliminates output stores */
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bool kill_z;
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bool kill_stencil;
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bool kill_samplemask;
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} ac_nir_lower_ps_early_options;
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bool
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ac_nir_lower_ps_early(nir_shader *nir, const ac_nir_lower_ps_early_options *options);
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/* This is a post-link pass. It shouldn't eliminate any code and it shouldn't affect shader_info
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* (those should be done in the early pass).
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*/
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typedef struct {
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enum amd_gfx_level gfx_level;
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enum radeon_family family;
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bool use_aco;
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/* System values. */
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bool bc_optimize_for_persp;
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bool bc_optimize_for_linear;
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/* Exports. */
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bool uses_discard;
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bool dcc_decompress_gfx11;
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bool alpha_to_coverage_via_mrtz;
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bool dual_src_blend_swizzle;
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unsigned spi_shader_col_format;
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unsigned color_is_int8;
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unsigned color_is_int10;
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bool alpha_to_one;
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/* Vulkan only */
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unsigned enable_mrt_output_nan_fixup;
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bool no_color_export;
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bool no_depth_export;
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} ac_nir_lower_ps_late_options;
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bool
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ac_nir_lower_ps_late(nir_shader *nir, const ac_nir_lower_ps_late_options *options);
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typedef struct {
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enum amd_gfx_level gfx_level;
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/* If true, round the layer component of the coordinates source to the nearest
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* integer for all array ops. This is always done for cube array ops.
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*/
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bool lower_array_layer_round_even;
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/* Fix derivatives of constants and FS inputs in control flow.
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*
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* Ignores interpolateAtSample()/interpolateAtOffset(), dynamically indexed input loads,
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* pervertexEXT input loads, textureGather() with implicit LOD and 16-bit derivatives and
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* texture samples with nir_tex_src_min_lod.
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*
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* The layer must also be a constant or FS input.
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*/
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bool fix_derivs_in_divergent_cf;
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unsigned max_wqm_vgprs;
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} ac_nir_lower_tex_options;
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bool
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ac_nir_lower_tex(nir_shader *nir, const ac_nir_lower_tex_options *options);
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void
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ac_nir_store_debug_log_amd(nir_builder *b, nir_def *uvec4);
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bool
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ac_nir_opt_pack_half(nir_shader *shader, enum amd_gfx_level gfx_level);
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unsigned
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ac_nir_varying_expression_max_cost(nir_shader *producer, nir_shader *consumer);
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bool
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ac_nir_opt_shared_append(nir_shader *shader);
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bool
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ac_nir_flag_smem_for_loads(nir_shader *shader, enum amd_gfx_level gfx_level, bool use_llvm, bool after_lowering);
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bool
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ac_nir_lower_mem_access_bit_sizes(nir_shader *shader, enum amd_gfx_level gfx_level, bool use_llvm);
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bool
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ac_nir_optimize_uniform_atomics(nir_shader *nir);
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unsigned
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ac_nir_lower_bit_size_callback(const nir_instr *instr, void *data);
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bool
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ac_nir_might_lower_bit_size(const nir_shader *shader);
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bool
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ac_nir_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size,
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unsigned num_components, int64_t hole_size,
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nir_intrinsic_instr *low, nir_intrinsic_instr *high, void *data);
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bool
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ac_nir_scalarize_overfetching_loads_callback(const nir_instr *instr, const void *data);
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enum gl_access_qualifier
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ac_nir_get_mem_access_flags(const nir_intrinsic_instr *instr);
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#ifdef __cplusplus
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}
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#endif
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#endif /* AC_NIR_H */
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