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b01d286083
Constructing the render target store payload is more complex than we can reasonably handle at the NIR level. The main reason is that samplemask and stencil are packed 16-bit and 8-bit parameters, respectively, which are intermixed with other values that are 32-bit. In SIMD32 mode, the packed sub-32-bit values take up fewer registers than normal values. Currently we also don't specialize the NIR for each FS dispatch width, and we can't construct the message descriptor without knowing it. So, we alter nir_intrinsic_store_render_target_intel to take each of the expected parameters - colour, depth, stencil, samplemask, src0_alpha, and discard predicate. We construct the payloads and descriptors in the backend. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688> |
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