Eric Anholt ac0051a507 gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4. ... Because vc4 can control the order that tiles are rasterized in, we can use it to implement overlapping blits using normal drawing and GL_ARB_texture_barrier, as long as we can tell the kernel what order to render the tiles in. This commit introduces the core gallium support, vc4 changes will follow. v2: Fix on the simulator. v3: Add the cap (disabled) to other drivers, add rst docs for the cap. v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS v5: Drop vc4 changes from this commit, for clarity. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)		2017-10-10 10:45:22 -07:00
..
amd	radv: export KHR_relaxed_block_layout	2017-10-10 13:22:44 +10:00
broadcom	broadcom: Fix out-of-tree build include path	2017-10-05 15:03:11 -07:00
compiler	glsl/linker: add check for compute shared memory size	2017-10-10 13:58:43 +02:00
egl	egl/dri: remove old left-overs	2017-10-10 13:58:47 +02:00
gallium	gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.	2017-10-10 10:45:22 -07:00
gbm	meson: build gbm	2017-10-09 13:42:44 -07:00
getopt
glx	meson: Add support for configuring dri drivers directory.	2017-10-09 13:42:44 -07:00
gtest	meson: convert gtest to an internal dependency	2017-10-03 10:02:08 -07:00
hgl
intel	i965/tes: account for the fact that dvec3/4 inputs take two slots	2017-10-10 08:59:54 +02:00
loader	meson: build glx	2017-10-09 13:42:44 -07:00
mapi	meson: build glx	2017-10-09 13:42:44 -07:00
mesa	mesa: move _mesa_half_is_negative() to half_float.h	2017-10-10 11:28:31 -06:00
util	mesa: move _mesa_half_is_negative() to half_float.h	2017-10-10 11:28:31 -06:00
vulkan	vulkan: util: add macros to extract extension/offset number from enums	2017-10-06 11:45:41 +01:00
git_sha1.h.in	meson: Build i965 and dri stack	2017-10-09 13:42:44 -07:00
Makefile.am	automake: adjust wayland-drm comment	2017-09-19 19:02:34 +01:00
meson.build	meson: build gbm	2017-10-09 13:42:44 -07:00
SConscript	scons: use python3-compatible print()	2017-09-25 11:57:12 +01:00