Daniel Schürmann cf13a1d791 radv/rt: Fix and improve VkPipelineCreationFeedback ... Due to a copy-paste error, we asserted pipelineStageCreationFeedbackCount == 1 and wrote the stage feedback of the combined shader into the feedback of the first stage. This is fixed. Instead, we now write the precompilation feedback for each stage. This not ideal, but definitely an improvement. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22100>		2023-05-02 19:15:10 +00:00
..
addrlib	amd: update addrlib	2023-03-29 20:36:09 +00:00
ci	radv/ci: document another vkcts flake on vega10	2023-04-26 08:32:56 +00:00
common	ac/nir: fix 8-bit/10-bit PS exports clamping	2023-04-28 17:38:06 +00:00
compiler	aco: allow no export instruction for gfx10+ fs	2023-04-28 11:33:28 +08:00
drm-shim	amd: fix typos	2023-04-13 23:08:22 +00:00
llvm	aco,ac/llvm,radv,radeonsi: handle ps bc optimization in nir for radv	2023-04-26 03:27:26 +00:00
registers	amd/registers: use gfx9 packet definitions for gfx940	2023-04-06 15:00:54 +00:00
vulkan	radv/rt: Fix and improve VkPipelineCreationFeedback	2023-05-02 19:15:10 +00:00
.clang-format	amd: Add radv_foreach_stage to ForEachMacros.	2023-03-27 08:29:35 +00:00
meson.build	meson: build radeon drm-shim also for r300 and r600	2022-11-16 14:37:47 +00:00