mesa/src/intel
Rafael Antognolli a026d2d11c intel/compiler: Assert that unsupported tg4 offsets were lowered for XeHP
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14142>
2021-12-13 16:59:44 -08:00
..
blorp intel/blorp: Modify get_fast_clear_rect for XeHP 2021-12-11 04:14:20 +00:00
common intel/l3: Make DG1 urb-size exception more generic 2021-12-11 00:09:50 +00:00
compiler intel/compiler: Assert that unsupported tg4 offsets were lowered for XeHP 2021-12-13 16:59:44 -08:00
dev intel/dev: Add gtt_size to devinfo 2021-12-11 05:05:19 +00:00
ds intel: move timestamp scaling helper to intel/perf 2021-11-22 11:52:46 +00:00
genxml genxml: protect _length defines in genX_bits.h 2021-12-06 08:02:59 +00:00
isl intel/isl: Require aux map for some 64K alignment 2021-12-11 04:14:20 +00:00
nullhw-layer intel/nullhw: fix build 2021-03-26 20:12:40 +00:00
perf intel: move timestamp scaling helper to intel/perf 2021-11-22 11:52:46 +00:00
tools intel/stub: Implement I915_PARAM_HAS_USERPTR_PROBE 2021-12-09 10:57:57 -08:00
vulkan anv: Align buffer VMA to 2MiB for XeHP 2021-12-13 22:29:18 +00:00
Makefile.perf.am intel: Rename GEN_PERF prefix to INTEL_PERF in build files 2021-04-20 20:06:34 +00:00
meson.build pps: Intel pps driver 2021-05-18 14:28:48 +00:00