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If a set layout is missing the driver can't compute the dynamic buffer start offsets correctly. The only solution is to load these offsets from an user SGPR. To avoid adding more complexity, these offsets are re-emitted every time dynamic buffers are dirty. That shouldn't matter because the combination of dynamic buffers and independent sets is just super rare. This fixes new VKCTS coverage dEQP-VK.pipeline.pipeline_library.graphics_library.independent_sets_random.*. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39988>
147 lines
4 KiB
C
147 lines
4 KiB
C
/*
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* Copyright © 2019 Valve Corporation.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_SHADER_ARGS_H
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#define RADV_SHADER_ARGS_H
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#include "compiler/shader_enums.h"
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#include "util/list.h"
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#include "util/macros.h"
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#include "ac_shader_args.h"
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#include "amd_family.h"
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#include "radv_constants.h"
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enum radv_ud_index {
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AC_UD_SCRATCH_RING_OFFSETS = 0,
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AC_UD_PUSH_CONSTANTS = 1,
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AC_UD_INLINE_PUSH_CONSTANTS = 2,
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AC_UD_INDIRECT_DESCRIPTORS = 3,
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AC_UD_VIEW_INDEX = 4,
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AC_UD_STREAMOUT_BUFFERS = 5,
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AC_UD_STREAMOUT_STATE = 6,
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AC_UD_TASK_STATE = 7,
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AC_UD_NGGC_SETTINGS = 8,
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AC_UD_NGGC_VIEWPORT = 9,
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AC_UD_NGG_LDS_LAYOUT = 10,
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AC_UD_NGG_STATE = 11,
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AC_UD_NGG_QUERY_BUF_VA = 12,
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AC_UD_VGT_ESGS_RING_ITEMSIZE = 13,
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AC_UD_FORCE_VRS_RATES = 14,
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AC_UD_TASK_RING_ENTRY = 15,
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AC_UD_NEXT_STAGE_PC = 16,
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AC_UD_EPILOG_PC = 17,
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AC_UD_DYNAMIC_DESCRIPTORS = 18,
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AC_UD_DYNAMIC_DESCRIPTORS_OFFSET_ADDR = 19,
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AC_UD_SHADER_START = 20,
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AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
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AC_UD_VS_BASE_VERTEX_START_INSTANCE,
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AC_UD_VS_PROLOG_INPUTS,
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AC_UD_VS_MAX_UD,
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AC_UD_PS_STATE,
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AC_UD_PS_MAX_UD,
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AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
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AC_UD_CS_SBT_DESCRIPTORS,
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AC_UD_CS_RAY_LAUNCH_SIZE_ADDR,
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AC_UD_CS_RAY_DYNAMIC_CALLABLE_STACK_BASE,
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AC_UD_CS_TRAVERSAL_SHADER_ADDR,
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AC_UD_CS_TASK_RING_OFFSETS,
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AC_UD_CS_TASK_DRAW_ID,
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AC_UD_CS_TASK_IB,
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AC_UD_CS_MAX_UD,
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AC_UD_GS_MAX_UD,
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AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
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AC_UD_TCS_MAX_UD,
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/* We might not know the previous stage when compiling a geometry shader, so we just
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* declare both TES and VS user SGPRs.
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*/
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AC_UD_TES_MAX_UD = AC_UD_TCS_MAX_UD,
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AC_UD_MAX_UD = AC_UD_CS_MAX_UD,
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};
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struct radv_userdata_info {
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int8_t sgpr_idx;
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uint8_t num_sgprs;
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};
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struct radv_userdata_locations {
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struct radv_userdata_info descriptor_sets[MAX_SETS];
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struct radv_userdata_info shader_data[AC_UD_MAX_UD];
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uint32_t descriptor_sets_enabled;
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};
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struct radv_shader_args {
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struct ac_shader_args ac;
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struct ac_arg descriptors[MAX_SETS];
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/* Streamout */
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struct ac_arg streamout_buffers;
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struct ac_arg streamout_state; /* GFX12+ */
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/* Task */
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struct ac_arg task_state;
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/* User data 2/3. same as ring_offsets but for task shaders. */
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struct ac_arg task_ring_offsets;
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/* NGG */
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struct ac_arg ngg_state;
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struct ac_arg ngg_lds_layout;
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struct ac_arg ngg_query_buf_va; /* GFX11+ */
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/* NGG Culling */
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struct ac_arg nggc_settings;
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struct ac_arg nggc_viewport_scale[2];
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struct ac_arg nggc_viewport_translate[2];
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/* Fragment shaders */
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struct ac_arg ps_state;
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struct ac_arg prolog_inputs;
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struct ac_arg vs_inputs[MAX_VERTEX_ATTRIBS];
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/* PS epilogs */
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struct ac_arg colors[MAX_RTS];
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struct ac_arg depth;
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struct ac_arg stencil;
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struct ac_arg sample_mask;
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/* GS */
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struct ac_arg vgt_esgs_ring_itemsize;
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/* For non-monolithic VS or TES on GFX9+. */
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struct ac_arg next_stage_pc;
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/* PS/TCS epilogs PC. */
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struct ac_arg epilog_pc;
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struct radv_userdata_locations user_sgprs_locs;
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unsigned num_user_sgprs;
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bool explicit_scratch_args;
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bool remap_spi_ps_input;
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};
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static inline struct radv_shader_args *
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radv_shader_args_from_ac(struct ac_shader_args *args)
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{
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return container_of(args, struct radv_shader_args, ac);
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}
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struct radv_graphics_state_key;
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struct radv_shader_info;
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struct radv_ps_epilog_key;
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struct radv_device;
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void radv_declare_shader_args(const struct radv_device *device, const struct radv_graphics_state_key *gfx_state,
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const struct radv_shader_info *info, mesa_shader_stage stage,
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mesa_shader_stage previous_stage, struct radv_shader_args *args);
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void radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_ps_epilog_key *key,
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struct radv_shader_args *args);
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void radv_declare_rt_shader_args(enum amd_gfx_level gfx_level, struct radv_shader_args *args);
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#endif /* RADV_SHADER_ARGS_H */
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