Bas Nieuwenhuizen cf6a14de0c radv: Set RB+ registers correctly without framebuffer. ... Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13699>		2021-11-24 18:22:10 +00:00
..
addrlib	amd/addrlib: Use get_supported_arguments to get compiler args.	2021-11-24 07:03:54 +00:00
ci	ac: change family names to uppercase in ac_get_family_name()	2021-11-23 08:07:41 +00:00
common	ac/surface: allow gfx6-8 to enter the gfx9 DCC codepath for SI_FORCE_FAMILY	2021-11-24 13:55:23 +00:00
compiler	aco/spill: use spills_entry instead of spills_exit to kill linear VGPRs	2021-11-22 19:46:22 +00:00
llvm	nir: Rename nir_get_io_vertex_index_src and include per-primitive I/O.	2021-11-16 07:46:55 +00:00
registers	python: drop python2 support	2021-08-14 21:44:32 +00:00
vulkan	radv: Set RB+ registers correctly without framebuffer.	2021-11-24 18:22:10 +00:00
.clang-format	radv: Add clang-format for AMD code.	2021-04-10 03:31:32 +02:00
meson.build	radv: Allow building when LLVM isn’t enabled	2021-10-01 10:40:18 +02:00