José Roberto de Souza a65e982b44 anv: Split ANV_BO_ALLOC_HOST_CACHED_COHERENT into two actual flags ... As suggested by Lionel, here adding ANV_BO_ALLOC_HOST_COHERENT and with that ANV_BO_ALLOC_HOST_CACHED_COHERENT is now defined by (ANV_BO_ALLOC_HOST_COHERENT | ANV_BO_ALLOC_HOST_CACHED). In some callers of anv_device_alloc_bo() was necessary to add ANV_BO_ALLOC_HOST_COHERENT as no other flag was set and that was the default behavior up to now. A change that could look not related is the removal of the intel_flush_range() in anv_device_init_trivial_batch(), that was done because trivial_batch_bo is HOST_COHERENT so no flush is necessary. And it did not made sense to make it ANV_BO_ALLOC_HOST_CACHED_COHERENT as it was never read in CPU. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>		2023-12-06 22:18:26 +00:00
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anv_batch_chain.c	intel: Sync xe_drm.h take 2 part 3	2023-12-06 17:35:23 +00:00
anv_batch_chain.h	anv/trtt: add struct anv_trtt_batch_bo and pass it around	2023-11-17 17:58:29 +00:00
anv_device.c	anv: Add heaps for Xe KMD in platforms without LLC	2023-11-29 14:57:42 +00:00
anv_device.h	anv: hide exec_flags selection inside the i915 backend	2023-07-13 17:12:26 +00:00
anv_kmd_backend.c	anv: Split ANV_BO_ALLOC_HOST_CACHED_COHERENT into two actual flags	2023-12-06 22:18:26 +00:00
anv_queue.c	intel: Sync xe_drm.h take 2 part 3	2023-12-06 17:35:23 +00:00
anv_queue.h	anv: Create Xe engines	2023-03-23 13:27:39 +00:00