mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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74f1d4f47b
Minor adjustments to formatting of the copyright line, but keep dates and holders. "Authors" entries that could be obtained via Git logs were also removed. The license in brw_disasm.c and elk_disasm.c don't match directly any SPDX pattern I could find, so kept as is. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39503>
579 lines
22 KiB
C++
579 lines
22 KiB
C++
/*
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* Copyright © 2015 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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/** @file
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*
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* Implements a pass that validates various invariants of the IR. The current
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* pass only validates that GRF's uses are sane. More can be added later.
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*/
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#include "brw_shader.h"
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#include "brw_cfg.h"
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#include "brw_eu.h"
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#ifndef NDEBUG
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static void
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brw_validate_abort_with_message_fmt(const brw_shader &s,
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const brw_inst *inst,
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const char *filename,
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unsigned line,
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const char *fmt, ...)
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{
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fprintf(stderr,
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"ASSERT: BRW %s validation failed!\n",
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_mesa_shader_stage_to_abbrev(s.stage));
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brw_print_instruction(s, inst, stderr);
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fprintf(stderr, "%s:%d: ", filename, line);
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va_list args;
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va_start(args, fmt);
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vfprintf(stderr, fmt, args);
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va_end(args);
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fputc('\n', stderr);
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abort();
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}
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#define VAL_ASSERT(assertion) \
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if (!(assertion)) { \
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brw_validate_abort_with_message_fmt( \
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s, inst, __FILE__, __LINE__, \
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"'%s' failed\n", #assertion); \
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}
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#define VAL_ASSERT_CMP(A, COMPARATOR, B) \
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{ \
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const uintptr_t a = uintptr_t(A); \
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const uintptr_t b = uintptr_t(B); \
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if (!(a COMPARATOR b)) { \
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brw_validate_abort_with_message_fmt( \
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s, inst, __FILE__, __LINE__, \
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"A %s B failed\n" \
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" A = %s = %" PRIuPTR "\n" \
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" B = %s = %" PRIuPTR "\n", \
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#COMPARATOR, #A, a, #B, b); \
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} \
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}
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#define VAL_ASSERT_EQ(A, B) VAL_ASSERT_CMP(A, ==, B)
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#define VAL_ASSERT_NE(A, B) VAL_ASSERT_CMP(A, !=, B)
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#define VAL_ASSERT_LT(A, B) VAL_ASSERT_CMP(A, <, B)
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#define VAL_ASSERT_LE(A, B) VAL_ASSERT_CMP(A, <=, B)
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#define VAL_ASSERT_GT(A, B) VAL_ASSERT_CMP(A, >, B)
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#define VAL_ASSERT_GE(A, B) VAL_ASSERT_CMP(A, >=, B)
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static inline bool
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is_ud_imm(const brw_reg ®)
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{
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return reg.file == IMM && reg.type == BRW_TYPE_UD;
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}
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static void
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validate_memory_logical(const brw_shader &s, const brw_mem_inst *inst)
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{
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const intel_device_info *devinfo = s.devinfo;
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enum lsc_opcode op = inst->lsc_op;
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enum memory_flags flags = (memory_flags)inst->flags;
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bool transpose = flags & MEMORY_FLAG_TRANSPOSE;
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bool include_helpers = flags & MEMORY_FLAG_INCLUDE_HELPERS;
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enum memory_logical_mode mode = inst->mode;
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enum lsc_data_size data_size = inst->data_size;
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unsigned data_size_B = lsc_data_size_bytes(data_size);
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if (!devinfo->has_lsc) {
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VAL_ASSERT(data_size == LSC_DATA_SIZE_D8U32 ||
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data_size == LSC_DATA_SIZE_D16U32 ||
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data_size == LSC_DATA_SIZE_D32 ||
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data_size == LSC_DATA_SIZE_D64);
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if (transpose) {
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const unsigned min_alignment =
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mode == MEMORY_MODE_SHARED_LOCAL ? 16 : 4;
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VAL_ASSERT_GE(inst->alignment, min_alignment);
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}
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}
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VAL_ASSERT(!transpose || !include_helpers);
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VAL_ASSERT(!transpose || lsc_opcode_has_transpose(op));
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if (inst->binding_type == LSC_ADDR_SURFTYPE_FLAT)
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VAL_ASSERT_EQ(inst->src[MEMORY_LOGICAL_BINDING].file, BAD_FILE);
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if (inst->src[MEMORY_LOGICAL_DATA1].file != BAD_FILE) {
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VAL_ASSERT_EQ(inst->components,
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inst->components_read(MEMORY_LOGICAL_DATA1));
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VAL_ASSERT_EQ(inst->src[MEMORY_LOGICAL_DATA0].type,
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inst->src[MEMORY_LOGICAL_DATA1].type);
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}
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if (inst->src[MEMORY_LOGICAL_DATA0].file != BAD_FILE) {
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VAL_ASSERT_EQ(inst->components,
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inst->components_read(MEMORY_LOGICAL_DATA0));
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VAL_ASSERT_EQ(brw_type_size_bytes(inst->src[MEMORY_LOGICAL_DATA0].type),
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data_size_B);
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}
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if (inst->dst.file != BAD_FILE)
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VAL_ASSERT_EQ(brw_type_size_bytes(inst->dst.type), data_size_B);
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/** TGM messages cannot have a base offset */
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if (mode == MEMORY_MODE_TYPED)
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VAL_ASSERT_EQ(inst->as_mem()->address_offset, 0);
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/* Offset must be DWord aligned */
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VAL_ASSERT_EQ((inst->as_mem()->address_offset % 4), 0);
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switch (inst->opcode) {
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case SHADER_OPCODE_MEMORY_LOAD_LOGICAL:
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VAL_ASSERT(op == LSC_OP_LOAD || op == LSC_OP_LOAD_CMASK ||
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op == LSC_OP_LOAD_CMASK_MSRT);
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VAL_ASSERT_EQ(inst->src[MEMORY_LOGICAL_DATA0].file, BAD_FILE);
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VAL_ASSERT_EQ(inst->src[MEMORY_LOGICAL_DATA1].file, BAD_FILE);
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break;
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case SHADER_OPCODE_MEMORY_STORE_LOGICAL:
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VAL_ASSERT(lsc_opcode_is_store(op));
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VAL_ASSERT_NE(inst->src[MEMORY_LOGICAL_DATA0].file, BAD_FILE);
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VAL_ASSERT_EQ(inst->src[MEMORY_LOGICAL_DATA1].file, BAD_FILE);
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break;
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case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL:
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VAL_ASSERT(lsc_opcode_is_atomic(op));
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VAL_ASSERT_EQ((inst->src[MEMORY_LOGICAL_DATA0].file == BAD_FILE),
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(lsc_op_num_data_values(op) < 1));
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VAL_ASSERT_EQ((inst->src[MEMORY_LOGICAL_DATA1].file == BAD_FILE),
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(lsc_op_num_data_values(op) < 2));
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VAL_ASSERT_EQ(inst->components, 1);
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VAL_ASSERT(!include_helpers);
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break;
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default:
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UNREACHABLE("invalid opcode");
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}
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}
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static const char *
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brw_shader_phase_to_string(enum brw_shader_phase phase)
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{
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switch (phase) {
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case BRW_SHADER_PHASE_INITIAL: return "INITIAL";
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case BRW_SHADER_PHASE_AFTER_NIR: return "AFTER_NIR";
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case BRW_SHADER_PHASE_AFTER_OPT_LOOP: return "AFTER_OPT_LOOP";
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case BRW_SHADER_PHASE_AFTER_EARLY_LOWERING: return "AFTER_EARLY_LOWERING";
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case BRW_SHADER_PHASE_AFTER_MIDDLE_LOWERING: return "AFTER_MIDDLE_LOWERING";
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case BRW_SHADER_PHASE_AFTER_LATE_LOWERING: return "AFTER_LATE_LOWERING";
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case BRW_SHADER_PHASE_AFTER_REGALLOC: return "AFTER_REGALLOC";
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case BRW_SHADER_PHASE_INVALID: break;
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}
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UNREACHABLE("invalid_phase");
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return NULL;
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}
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static void
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brw_validate_instruction_phase(const brw_shader &s, brw_inst *inst)
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{
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enum brw_shader_phase invalid_from = BRW_SHADER_PHASE_INVALID;
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switch (inst->opcode) {
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case FS_OPCODE_FB_WRITE_LOGICAL:
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case FS_OPCODE_FB_READ_LOGICAL:
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case SHADER_OPCODE_SAMPLER:
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case SHADER_OPCODE_MEMORY_LOAD_LOGICAL:
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case SHADER_OPCODE_MEMORY_STORE_LOGICAL:
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case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL:
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case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
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case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
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case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
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case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
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case SHADER_OPCODE_BTD_SPAWN_LOGICAL:
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case SHADER_OPCODE_BTD_RETIRE_LOGICAL:
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case RT_OPCODE_TRACE_RAY_LOGICAL:
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case SHADER_OPCODE_URB_READ_LOGICAL:
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case SHADER_OPCODE_URB_WRITE_LOGICAL:
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case SHADER_OPCODE_REDUCE:
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case SHADER_OPCODE_INCLUSIVE_SCAN:
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case SHADER_OPCODE_EXCLUSIVE_SCAN:
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case SHADER_OPCODE_VOTE_ANY:
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case SHADER_OPCODE_VOTE_ALL:
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case SHADER_OPCODE_VOTE_EQUAL:
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case SHADER_OPCODE_BALLOT:
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case SHADER_OPCODE_QUAD_SWAP:
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case SHADER_OPCODE_READ_FROM_LIVE_CHANNEL:
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case SHADER_OPCODE_READ_FROM_CHANNEL:
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case SHADER_OPCODE_LOAD_REG:
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invalid_from = BRW_SHADER_PHASE_AFTER_EARLY_LOWERING;
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break;
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case SHADER_OPCODE_LOAD_PAYLOAD:
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invalid_from = BRW_SHADER_PHASE_AFTER_MIDDLE_LOWERING;
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break;
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default:
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/* Nothing to do. */
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break;
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}
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assert(s.phase < BRW_SHADER_PHASE_INVALID);
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if (s.phase >= invalid_from) {
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fprintf(stderr, "INVALID INSTRUCTION IN PHASE: %s\n",
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brw_shader_phase_to_string(s.phase));
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brw_print_instruction(s, inst, stderr);
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abort();
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}
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}
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void
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brw_validate(const brw_shader &s)
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{
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const intel_device_info *devinfo = s.devinfo;
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if (!s.cfg)
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return;
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s.cfg->validate(_mesa_shader_stage_to_abbrev(s.stage));
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foreach_block(block, s.cfg) {
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/* Track the last used address register. Usage of the address register
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* in the IR should be limited to within a block, otherwise we would
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* unable to schedule some instructions without spilling the address
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* register to a VGRF.
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*
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* Another pattern we stick to when using the address register in the IR
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* is that we write and read the register in pairs of instruction.
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*/
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uint32_t last_used_address_register[16] = {};
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foreach_inst_in_block (brw_inst, inst, block) {
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VAL_ASSERT_EQ(inst->kind, brw_inst_kind_for_opcode(inst->opcode));
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brw_validate_instruction_phase(s, inst);
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switch (inst->opcode) {
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case SHADER_OPCODE_SEND:
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VAL_ASSERT_EQ(inst->sources, SEND_NUM_SRCS);
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VAL_ASSERT(is_uniform(inst->src[SEND_SRC_DESC]));
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VAL_ASSERT(is_uniform(inst->src[SEND_SRC_EX_DESC]));
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VAL_ASSERT_NE(inst->src[SEND_SRC_PAYLOAD1].file, BAD_FILE);
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VAL_ASSERT(inst->as_send()->ex_mlen > 0 ||
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inst->src[SEND_SRC_PAYLOAD2].file == BAD_FILE);
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/* Send payloads cannot be immediates nor have source modifiers */
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for (unsigned i = 0; i < 2; i++) {
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VAL_ASSERT_NE(inst->src[SEND_SRC_PAYLOAD1 + i].file, IMM);
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VAL_ASSERT(!inst->src[SEND_SRC_PAYLOAD1 + i].abs);
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VAL_ASSERT(!inst->src[SEND_SRC_PAYLOAD1 + i].negate);
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}
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break;
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case SHADER_OPCODE_SEND_GATHER:
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VAL_ASSERT(is_uniform(inst->src[0]) && is_uniform(inst->src[1]));
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VAL_ASSERT_GE(devinfo->ver, 30);
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break;
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case BRW_OPCODE_MOV:
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VAL_ASSERT_EQ(inst->sources, 1);
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break;
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case SHADER_OPCODE_MEMORY_LOAD_LOGICAL:
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case SHADER_OPCODE_MEMORY_STORE_LOGICAL:
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case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL:
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validate_memory_logical(s, inst->as_mem());
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break;
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case SHADER_OPCODE_MEMORY_FENCE:
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case SHADER_OPCODE_INTERLOCK:
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VAL_ASSERT_EQ(inst->exec_size, 1);
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VAL_ASSERT(inst->force_writemask_all);
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VAL_ASSERT_EQ(inst->sources, 2);
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VAL_ASSERT(is_ud_imm(inst->src[1])); /* commit enable */
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break;
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case SHADER_OPCODE_LOAD_REG: {
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VAL_ASSERT_EQ(inst->sources, 1);
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VAL_ASSERT_EQ(s.alloc.sizes[inst->dst.nr] * REG_SIZE, inst->size_written);
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VAL_ASSERT(!inst->is_partial_write());
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VAL_ASSERT_LE(inst->src[0].stride, 1);
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/* For example, if file == UNIFORM, stride will be zero and offset
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* may be non-zero.
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*/
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if (inst->src[0].stride != 0)
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VAL_ASSERT_EQ(inst->src[0].offset, 0);
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const brw_def_analysis &defs = s.def_analysis.require();
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VAL_ASSERT_EQ(inst, defs.get(inst->dst));
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break;
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}
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case BRW_OPCODE_BFN:
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VAL_ASSERT(!inst->src[0].abs && !inst->src[0].negate);
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VAL_ASSERT(!inst->src[1].abs && !inst->src[1].negate);
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VAL_ASSERT(!inst->src[2].abs && !inst->src[2].negate);
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VAL_ASSERT_EQ(inst->src[3].file, IMM);
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/* BFN only supports a limited subset of conditions. */
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VAL_ASSERT(inst->conditional_mod == BRW_CONDITIONAL_NONE ||
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inst->conditional_mod == BRW_CONDITIONAL_Z ||
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inst->conditional_mod == BRW_CONDITIONAL_G ||
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inst->conditional_mod == BRW_CONDITIONAL_L);
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break;
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default:
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break;
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}
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/* On Xe2, the "write the accumulator in addition to the explicit
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* destination" bit no longer exists. Try to catch uses of this
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* feature earlier in the process.
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*/
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if (devinfo->ver >= 20 && inst->writes_accumulator) {
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VAL_ASSERT(inst->dst.is_accumulator() ||
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inst->opcode == BRW_OPCODE_ADDC ||
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inst->opcode == BRW_OPCODE_MACH ||
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inst->opcode == BRW_OPCODE_SUBB);
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}
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if (inst->is_3src(s.compiler)) {
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const unsigned integer_sources =
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brw_type_is_int(inst->src[0].type) +
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brw_type_is_int(inst->src[1].type) +
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brw_type_is_int(inst->src[2].type);
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const unsigned float_sources =
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brw_type_is_float_or_bfloat(inst->src[0].type) +
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brw_type_is_float_or_bfloat(inst->src[1].type) +
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brw_type_is_float_or_bfloat(inst->src[2].type);
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VAL_ASSERT((integer_sources == 3 && float_sources == 0) ||
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(integer_sources == 0 && float_sources == 3));
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if (devinfo->ver >= 10) {
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for (unsigned i = 0; i < 3; i++) {
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if (inst->src[i].file == IMM)
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continue;
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switch (inst->src[i].vstride) {
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case BRW_VERTICAL_STRIDE_0:
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case BRW_VERTICAL_STRIDE_4:
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case BRW_VERTICAL_STRIDE_8:
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case BRW_VERTICAL_STRIDE_16:
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break;
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case BRW_VERTICAL_STRIDE_1:
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VAL_ASSERT_GE(devinfo->ver, 12);
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break;
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case BRW_VERTICAL_STRIDE_2:
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VAL_ASSERT_LE(devinfo->ver, 11);
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break;
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default:
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VAL_ASSERT(!"invalid vstride");
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break;
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}
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}
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} else if (s.grf_used != 0) {
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/* Only perform the pre-Gfx10 checks after register allocation
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* has occured.
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*
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* Many passes (e.g., constant copy propagation) will
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* genenerate invalid 3-source instructions with the
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* expectation that later passes (e.g., combine constants) will
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* fix them.
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*/
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for (unsigned i = 0; i < 3; i++) {
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VAL_ASSERT_NE(inst->src[i].file, IMM);
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/* A stride of 1 (the usual case) or 0, with a special
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* "repctrl" bit, is allowed. The repctrl bit doesn't work
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* for 64-bit datatypes, so if the source type is 64-bit
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* then only a stride of 1 is allowed. From the Broadwell
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* PRM, Volume 7 "3D Media GPGPU", page 944:
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*
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* This is applicable to 32b datatypes and 16b datatype.
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* 64b datatypes cannot use the replicate control.
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*/
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const unsigned stride_in_bytes = byte_stride(inst->src[i]);
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const unsigned size_in_bytes = brw_type_size_bytes(inst->src[i].type);
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if (stride_in_bytes == 0) {
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/* If the source is_scalar, then the stride will be
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* converted to <4;4,1> in brw_lower_scalar_fp64_MAD
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* after SIMD splitting.
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*/
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if (!inst->src[i].is_scalar)
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VAL_ASSERT_LE(size_in_bytes, 4);
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} else {
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VAL_ASSERT_EQ(stride_in_bytes, size_in_bytes);
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}
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}
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}
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}
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if (inst->dst.file == VGRF) {
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VAL_ASSERT_LE(inst->dst.offset / REG_SIZE + regs_written(inst),
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s.alloc.sizes[inst->dst.nr]);
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if (inst->exec_size > 1)
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VAL_ASSERT_NE(inst->dst.stride, 0);
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} else if (inst->dst.is_address()) {
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VAL_ASSERT_NE(inst->dst.nr, 0);
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}
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bool read_address_reg = false;
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for (unsigned i = 0; i < inst->sources; i++) {
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if (inst->src[i].file == VGRF) {
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VAL_ASSERT_LE(inst->src[i].offset / REG_SIZE + regs_read(devinfo, inst, i),
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s.alloc.sizes[inst->src[i].nr]);
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} else if (inst->src[i].is_address()) {
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VAL_ASSERT_NE(inst->src[i].nr, 0);
|
|
for (unsigned hw = 0; hw < inst->size_read(devinfo, i); hw += 2) {
|
|
VAL_ASSERT_EQ(inst->src[i].nr,
|
|
last_used_address_register[inst->src[i].address_slot(hw)]);
|
|
}
|
|
read_address_reg = true;
|
|
}
|
|
}
|
|
|
|
/* Accumulator Registers, bspec 47251:
|
|
*
|
|
* "When destination is accumulator with offset 0, destination
|
|
* horizontal stride must be 1."
|
|
*/
|
|
if (intel_needs_workaround(devinfo, 14014617373) &&
|
|
inst->dst.is_accumulator() &&
|
|
phys_subnr(devinfo, inst->dst) == 0) {
|
|
VAL_ASSERT_EQ(inst->dst.hstride, 1);
|
|
}
|
|
|
|
if (inst->is_math() && intel_needs_workaround(devinfo, 22016140776)) {
|
|
/* Wa_22016140776:
|
|
*
|
|
* Scalar broadcast on HF math (packed or unpacked) must not be
|
|
* used. Compiler must use a mov instruction to expand the
|
|
* scalar value to a vector before using in a HF (packed or
|
|
* unpacked) math operation.
|
|
*
|
|
* Since copy propagation knows about this restriction, nothing
|
|
* should be able to generate these invalid source strides. Detect
|
|
* potential problems sooner rather than later.
|
|
*/
|
|
if (devinfo->ver >= 20 && inst->writes_accumulator) {
|
|
VAL_ASSERT(inst->dst.is_accumulator() ||
|
|
inst->opcode == BRW_OPCODE_ADDC ||
|
|
inst->opcode == BRW_OPCODE_MACH ||
|
|
inst->opcode == BRW_OPCODE_SUBB);
|
|
}
|
|
|
|
if (inst->is_3src(s.compiler)) {
|
|
const unsigned integer_sources =
|
|
brw_type_is_int(inst->src[0].type) +
|
|
brw_type_is_int(inst->src[1].type) +
|
|
brw_type_is_int(inst->src[2].type);
|
|
const unsigned float_sources =
|
|
brw_type_is_float(inst->src[0].type) +
|
|
brw_type_is_float(inst->src[1].type) +
|
|
brw_type_is_float(inst->src[2].type);
|
|
|
|
VAL_ASSERT((integer_sources == 3 && float_sources == 0) ||
|
|
(integer_sources == 0 && float_sources == 3));
|
|
|
|
if (devinfo->ver >= 10) {
|
|
for (unsigned i = 0; i < 3; i++) {
|
|
if (inst->src[i].file == IMM)
|
|
continue;
|
|
|
|
switch (inst->src[i].vstride) {
|
|
case BRW_VERTICAL_STRIDE_0:
|
|
case BRW_VERTICAL_STRIDE_4:
|
|
case BRW_VERTICAL_STRIDE_8:
|
|
case BRW_VERTICAL_STRIDE_16:
|
|
break;
|
|
|
|
case BRW_VERTICAL_STRIDE_1:
|
|
VAL_ASSERT_GE(devinfo->ver, 12);
|
|
break;
|
|
|
|
case BRW_VERTICAL_STRIDE_2:
|
|
VAL_ASSERT_LE(devinfo->ver, 11);
|
|
break;
|
|
|
|
default:
|
|
VAL_ASSERT(!"invalid vstride");
|
|
break;
|
|
}
|
|
}
|
|
} else if (s.grf_used != 0) {
|
|
/* Only perform the pre-Gfx10 checks after register
|
|
* allocation has occured.
|
|
*
|
|
* Many passes (e.g., constant copy propagation) will
|
|
* genenerate invalid 3-source instructions with the
|
|
* expectation that later passes (e.g., combine constants)
|
|
* will fix them.
|
|
*/
|
|
for (unsigned i = 0; i < 3; i++) {
|
|
VAL_ASSERT_NE(inst->src[i].file, IMM);
|
|
|
|
/* A stride of 1 (the usual case) or 0, with a special
|
|
* "repctrl" bit, is allowed. The repctrl bit doesn't
|
|
* work for 64-bit datatypes, so if the source type is
|
|
* 64-bit then only a stride of 1 is allowed. From the
|
|
* Broadwell PRM, Volume 7 "3D Media GPGPU", page 944:
|
|
*
|
|
* This is applicable to 32b datatypes and 16b
|
|
* datatype. 64b datatypes cannot use the replicate
|
|
* control.
|
|
*/
|
|
const unsigned stride_in_bytes = byte_stride(inst->src[i]);
|
|
const unsigned size_in_bytes = brw_type_size_bytes(inst->src[i].type);
|
|
if (stride_in_bytes == 0) {
|
|
VAL_ASSERT_LE(size_in_bytes, 4);
|
|
} else {
|
|
VAL_ASSERT_EQ(stride_in_bytes, size_in_bytes);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (inst->dst.file == VGRF) {
|
|
VAL_ASSERT_LE(inst->dst.offset / REG_SIZE + regs_written(inst),
|
|
s.alloc.sizes[inst->dst.nr]);
|
|
}
|
|
|
|
for (unsigned i = 0; i < inst->sources; i++) {
|
|
VAL_ASSERT(inst->src[i].is_scalar ||
|
|
!is_uniform(inst->src[i]) ||
|
|
inst->src[i].type != BRW_TYPE_HF);
|
|
}
|
|
}
|
|
|
|
/* Update the last used address register. */
|
|
if (read_address_reg) {
|
|
/* When an instruction only reads the address register, we assume
|
|
* the read parts are never going to be used again.
|
|
*/
|
|
for (unsigned i = 0; i < inst->sources; i++) {
|
|
if (!inst->src[i].is_address())
|
|
continue;
|
|
for (unsigned hw = 0; hw < inst->size_read(devinfo, i); hw += 2)
|
|
last_used_address_register[inst->src[i].address_slot(hw)] = 0;
|
|
}
|
|
}
|
|
if (inst->dst.is_address()) {
|
|
/* For the written part of the address register */
|
|
for (unsigned hw = 0; hw < inst->size_written; hw += 2)
|
|
last_used_address_register[inst->dst.address_slot(hw)] = inst->dst.nr;
|
|
} else if (inst->uses_address_register_implicitly()) {
|
|
/* If the instruction is making use of the address register,
|
|
* discard the entire thing.
|
|
*/
|
|
memset(last_used_address_register, 0,
|
|
sizeof(last_used_address_register));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|