Danylo Piliaiev c1d5c318bc ir3: New cat3 instructions ... * shrm - (src2 >> src1) & src3 * shlm - (src2 << src1) & src3 * shrg - (src2 >> src1) | src3 * shlg - (src2 << src1) | src3 * andg - (src2 & src1) | src3 * dp2acc - dot product of two {i,u}8vec2 packed into SRC1 and SRC2, added to 32b SRC3 * dp4acc - dot product of two {i,u}8vec4 packed into SRC1 and SRC2, added to 32b SRC3 * wmm - vec4(x_1, x_2, x_3, x_4) * (y_1 + y_2 + y_3 + y_4), which is duplicated (1 << (SRC3 / 32)) times starting from DST register * wmm.accu - same as wmm but result is added to DST registers, however the first reg in each vec4 result is overwritten instead of accumulating. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13986>		2022-01-10 13:20:39 +02:00
..
encode.c	ir3: Add gen4 new subgroup instructions	2021-12-07 20:45:53 +00:00
ir3-cat0.xml	ir3: Make shift operand 64-bit.	2021-12-22 01:19:46 +00:00
ir3-cat1.xml	freedreno/isa: Add immed reg accessors	2021-10-15 15:52:33 +00:00
ir3-cat2.xml	ir3: Add support for (dis)assembling flat.b	2021-11-04 02:59:28 +00:00
ir3-cat3.xml	ir3: New cat3 instructions	2022-01-10 13:20:39 +02:00
ir3-cat4.xml	freedreno/isa: Convert to srcs/dsts	2021-06-23 17:20:29 +00:00
ir3-cat5.xml	ir3: Add gen4 new subgroup instructions	2021-12-07 20:45:53 +00:00
ir3-cat6.xml	ir3: Add gen4 new subgroup instructions	2021-12-07 20:45:53 +00:00
ir3-cat7.xml
ir3-common.xml	freedreno/isa: Fix ldg/stg "halfness"	2021-10-19 16:04:42 +00:00
ir3-disasm.c	freedreno/isa: decode: switch bitmask_t to BITSET_WORD's	2021-09-21 20:25:31 +00:00
ir3.xml	freedreno/isa: Convert to srcs/dsts	2021-06-23 17:20:29 +00:00
isa.h	freedreno/isa: decode: switch bitmask_t to BITSET_WORD's	2021-09-21 20:25:31 +00:00
meson.build	freedreno/isa: move isaspec to a new home	2021-09-21 20:25:31 +00:00