Juston Li dc7c1d989b radv: enable stippledBresenhamLines on GFX9 chips ... This isn't supposed to work nor does it match radeonsi but setting AUTO_RESET_CNTL=0 by default for GFX9 chips is what gets it passing linestrip CTS tests: dEQP-VK.rasterization.primitives.dynamic_stipple.bresenham_line_strip dEQP-VK.rasterization.primitives.dynamic_stipple_and_topology.bresenham_line_strip dEQP-VK.rasterization.primitives.dynamic_stipple_and_topology.bresenham_line_strip_wide dEQP-VK.rasterization.primitives.static_stipple.bresenham_line_strip Signed-off-by: Juston Li <justonli@google.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24623>		2023-12-07 19:10:15 +00:00
..
addrlib	amd/common: update addrlib for gfx11.5	2023-10-20 07:32:34 +00:00
ci	ci: drop containers, builds, and tests from post-merge pipeline	2023-12-06 08:26:04 +00:00
common	treewide: Avoid use align as variable, replace it with other names	2023-12-07 02:30:53 +00:00
compiler	radv: prepare the PS epilog key for exporting MRTZ on RDNA3	2023-12-06 11:49:31 +00:00
drm-shim	amd: rename GFX110x to NAVI31-33	2023-09-30 23:08:47 +00:00
llvm	fix: ac/llvm: LLVM 18: remove useless passes, partially removed upstream	2023-11-24 14:11:09 +00:00
registers	ac/registers: allow to parse GCVM_L2_PROTECTION_FAULT_STATUS	2023-10-30 08:10:22 +00:00
vpelib	amd,radeonsi: add libvpe	2023-12-01 00:23:38 +00:00
vulkan	radv: enable stippledBresenhamLines on GFX9 chips	2023-12-07 19:10:15 +00:00
meson.build	amd,radeonsi: add libvpe	2023-12-01 00:23:38 +00:00