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Use lds base load intrinsics in nir ngg lowering to get layout, left its calulation to driver. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18832>
194 lines
6.7 KiB
C
194 lines
6.7 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef AC_SHADER_UTIL_H
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#define AC_SHADER_UTIL_H
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#include "ac_binary.h"
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#include "amd_family.h"
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#include "compiler/nir/nir.h"
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#include "compiler/shader_enums.h"
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#include "util/format/u_format.h"
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#include <stdbool.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum ac_image_dim
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{
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ac_image_1d,
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ac_image_2d,
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ac_image_3d,
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ac_image_cube, // includes cube arrays
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ac_image_1darray,
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ac_image_2darray,
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ac_image_2dmsaa,
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ac_image_2darraymsaa,
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};
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struct ac_data_format_info {
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uint8_t element_size;
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uint8_t num_channels;
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uint8_t chan_byte_size;
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uint8_t chan_format;
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};
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enum ac_vs_input_alpha_adjust {
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AC_ALPHA_ADJUST_NONE = 0,
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AC_ALPHA_ADJUST_SNORM = 1,
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AC_ALPHA_ADJUST_SSCALED = 2,
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AC_ALPHA_ADJUST_SINT = 3,
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};
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struct ac_vtx_format_info {
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uint16_t dst_sel;
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uint8_t element_size;
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uint8_t num_channels;
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uint8_t chan_byte_size; /* 0 for packed formats */
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/* These last three are dependent on the family. */
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uint8_t has_hw_format;
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/* Index is number of channels minus one. Use any index for packed formats.
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* GFX6-8 is dfmt[0:3],nfmt[4:7].
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*/
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uint8_t hw_format[4];
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enum ac_vs_input_alpha_adjust alpha_adjust : 8;
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};
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struct ac_spi_color_formats {
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unsigned normal : 8;
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unsigned alpha : 8;
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unsigned blend : 8;
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unsigned blend_alpha : 8;
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};
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/* For ac_build_fetch_format.
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*
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* Note: FLOAT must be 0 (used for convenience of encoding in radeonsi).
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*/
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enum ac_fetch_format
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{
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AC_FETCH_FORMAT_FLOAT = 0,
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AC_FETCH_FORMAT_FIXED,
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AC_FETCH_FORMAT_UNORM,
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AC_FETCH_FORMAT_SNORM,
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AC_FETCH_FORMAT_USCALED,
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AC_FETCH_FORMAT_SSCALED,
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AC_FETCH_FORMAT_UINT,
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AC_FETCH_FORMAT_SINT,
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AC_FETCH_FORMAT_NONE,
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};
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enum ac_descriptor_type
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{
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AC_DESC_IMAGE,
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AC_DESC_FMASK,
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AC_DESC_SAMPLER,
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AC_DESC_BUFFER,
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AC_DESC_PLANE_0,
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AC_DESC_PLANE_1,
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AC_DESC_PLANE_2,
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};
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unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask,
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bool writes_mrt0_alpha);
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unsigned ac_get_cb_shader_mask(unsigned spi_shader_col_format);
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uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum amd_gfx_level gfx_level);
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unsigned ac_get_tbuffer_format(enum amd_gfx_level gfx_level, unsigned dfmt, unsigned nfmt);
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const struct ac_data_format_info *ac_get_data_format_info(unsigned dfmt);
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const struct ac_vtx_format_info *ac_get_vtx_format_info_table(enum amd_gfx_level level,
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enum radeon_family family);
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const struct ac_vtx_format_info *ac_get_vtx_format_info(enum amd_gfx_level level,
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enum radeon_family family,
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enum pipe_format fmt);
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enum ac_image_dim ac_get_sampler_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim dim,
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bool is_array);
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enum ac_image_dim ac_get_image_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim sdim,
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bool is_array);
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unsigned ac_get_fs_input_vgpr_cnt(const struct ac_shader_config *config,
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signed char *face_vgpr_index, signed char *ancillary_vgpr_index,
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signed char *sample_coverage_vgpr_index_ptr);
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void ac_choose_spi_color_formats(unsigned format, unsigned swap, unsigned ntype,
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bool is_depth, bool use_rbplus,
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struct ac_spi_color_formats *formats);
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void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_culling,
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bool uses_scratch, unsigned *late_alloc_wave64, unsigned *cu_mask);
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unsigned ac_compute_cs_workgroup_size(const uint16_t sizes[3], bool variable, unsigned max);
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unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage,
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unsigned tess_num_patches,
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unsigned tess_patch_in_vtx,
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unsigned tess_patch_out_vtx);
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unsigned ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size,
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unsigned es_verts, unsigned gs_inst_prims);
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unsigned ac_compute_ngg_workgroup_size(unsigned es_verts, unsigned gs_inst_prims,
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unsigned max_vtx_out, unsigned prim_amp_factor);
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void ac_set_reg_cu_en(void *cs, unsigned reg_offset, uint32_t value, uint32_t clear_mask,
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unsigned value_shift, const struct radeon_info *info,
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void set_sh_reg(void*, unsigned, uint32_t));
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void ac_get_scratch_tmpring_size(const struct radeon_info *info, bool compute,
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unsigned bytes_per_wave, unsigned *max_seen_bytes_per_wave,
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uint32_t *tmpring_size);
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unsigned
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ac_ngg_nogs_get_pervertex_lds_size(gl_shader_stage stage,
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unsigned shader_num_outputs,
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bool streamout_enabled,
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bool export_prim_id,
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bool has_user_edgeflags,
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bool can_cull,
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bool uses_instance_id,
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bool uses_primitive_id);
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unsigned
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ac_ngg_get_scratch_lds_size(gl_shader_stage stage,
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unsigned workgroup_size,
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unsigned wave_size,
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bool streamout_enabled,
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bool can_cull);
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#ifdef __cplusplus
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}
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#endif
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#endif
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