mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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37f7983bcc
This commit moves our storage image format conversion codegen into NIR
instead of doing it in the back-end. This has the advantage of letting
us run it through NIR's optimizer which is pretty effective at shrinking
things down. In the common case of rgba8, the number of instructions
emitted after NIR is done with it is half of what it was with the
lowering happening in the back-end. On the downside, the back-end's
lowering is able to directly use predicates and the NIR lowering has to
use IFs.
Shader-db results on Kaby Lake:
total instructions in shared programs: 15166910 -> 15166872 (<.01%)
instructions in affected programs: 5895 -> 5857 (-0.64%)
helped: 15
HURT: 0
Clearly, we don't have that much image_load_store happening in the
shaders in shader-db....
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
208 lines
8.4 KiB
C++
208 lines
8.4 KiB
C++
/*
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* Copyright © 2013-2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "isl/isl.h"
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#include "brw_fs_surface_builder.h"
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#include "brw_fs.h"
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using namespace brw;
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namespace brw {
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namespace surface_access {
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namespace {
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/**
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* Generate a logical send opcode for a surface message and return
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* the result.
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*/
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fs_reg
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emit_send(const fs_builder &bld, enum opcode opcode,
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const fs_reg &addr, const fs_reg &src, const fs_reg &surface,
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unsigned dims, unsigned arg, unsigned rsize,
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brw_predicate pred = BRW_PREDICATE_NONE)
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{
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/* Reduce the dynamically uniform surface index to a single
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* scalar.
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*/
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const fs_reg usurface = bld.emit_uniformize(surface);
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const fs_reg srcs[] = {
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addr, src, usurface, brw_imm_ud(dims), brw_imm_ud(arg)
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};
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const fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, rsize);
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fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs));
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inst->size_written = rsize * dst.component_size(inst->exec_size);
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inst->predicate = pred;
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return dst;
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}
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}
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/**
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* Emit an untyped surface read opcode. \p dims determines the number
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* of components of the address and \p size the number of components of
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* the returned value.
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*/
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fs_reg
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emit_untyped_read(const fs_builder &bld,
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const fs_reg &surface, const fs_reg &addr,
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unsigned dims, unsigned size,
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brw_predicate pred)
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{
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return emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
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addr, fs_reg(), surface, dims, size, size, pred);
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}
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/**
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* Emit an untyped surface write opcode. \p dims determines the number
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* of components of the address and \p size the number of components of
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* the argument.
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*/
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void
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emit_untyped_write(const fs_builder &bld, const fs_reg &surface,
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const fs_reg &addr, const fs_reg &src,
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unsigned dims, unsigned size,
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brw_predicate pred)
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{
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emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
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addr, src, surface, dims, size, 0, pred);
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}
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/**
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* Emit an untyped surface atomic opcode. \p dims determines the number
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* of components of the address and \p rsize the number of components of
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* the returned value (either zero or one).
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*/
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fs_reg
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emit_untyped_atomic(const fs_builder &bld,
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const fs_reg &surface, const fs_reg &addr,
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const fs_reg &src0, const fs_reg &src1,
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unsigned dims, unsigned rsize, unsigned op,
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brw_predicate pred)
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{
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/* FINISHME: Factor out this frequently recurring pattern into a
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* helper function.
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*/
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const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
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const fs_reg srcs[] = { src0, src1 };
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const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, n);
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bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
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return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
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addr, tmp, surface, dims, op, rsize, pred);
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}
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/**
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* Emit an untyped surface atomic float opcode. \p dims determines the
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* number of components of the address and \p rsize the number of
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* components of the returned value (either zero or one).
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*/
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fs_reg
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emit_untyped_atomic_float(const fs_builder &bld,
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const fs_reg &surface, const fs_reg &addr,
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const fs_reg &src0, const fs_reg &src1,
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unsigned dims, unsigned rsize, unsigned op,
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brw_predicate pred)
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{
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/* FINISHME: Factor out this frequently recurring pattern into a
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* helper function.
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*/
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const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
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const fs_reg srcs[] = { src0, src1 };
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const fs_reg tmp = bld.vgrf(src0.type, n);
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bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
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return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
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addr, tmp, surface, dims, op, rsize, pred);
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}
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/**
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* Emit a typed surface read opcode. \p dims determines the number of
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* components of the address and \p size the number of components of the
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* returned value.
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*/
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fs_reg
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emit_typed_read(const fs_builder &bld, const fs_reg &surface,
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const fs_reg &addr, unsigned dims, unsigned size)
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{
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return emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
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addr, fs_reg(), surface, dims, size, size);
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}
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/**
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* Emit a typed surface write opcode. \p dims determines the number of
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* components of the address and \p size the number of components of the
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* argument.
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*/
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void
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emit_typed_write(const fs_builder &bld, const fs_reg &surface,
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const fs_reg &addr, const fs_reg &src,
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unsigned dims, unsigned size)
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{
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emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
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addr, src, surface, dims, size, 0);
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}
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/**
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* Emit a typed surface atomic opcode. \p dims determines the number of
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* components of the address and \p rsize the number of components of
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* the returned value (either zero or one).
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*/
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fs_reg
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emit_typed_atomic(const fs_builder &bld, const fs_reg &surface,
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const fs_reg &addr,
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const fs_reg &src0, const fs_reg &src1,
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unsigned dims, unsigned rsize, unsigned op,
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brw_predicate pred)
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{
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/* FINISHME: Factor out this frequently recurring pattern into a
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* helper function.
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*/
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const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
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const fs_reg srcs[] = { src0, src1 };
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const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, n);
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bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
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return emit_send(bld, SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
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addr, tmp, surface, dims, op, rsize);
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}
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fs_reg
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emit_byte_scattered_read(const fs_builder &bld,
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const fs_reg &surface, const fs_reg &addr,
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unsigned dims, unsigned size,
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unsigned bit_size, brw_predicate pred)
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{
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return emit_send(bld, SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
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addr, fs_reg(), surface, dims, bit_size, size, pred);
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}
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void
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emit_byte_scattered_write(const fs_builder &bld, const fs_reg &surface,
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const fs_reg &addr, const fs_reg &src,
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unsigned dims,
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unsigned bit_size, brw_predicate pred)
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{
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emit_send(bld, SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
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addr, src, surface, dims, bit_size, 0, pred);
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}
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}
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}
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