Sonny Jiang 2618886600 winsys/amdgpu: addrlib - port a Fiji bug fix ... Fiji: Fixed tiled resource failures Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> v2: fix a compile failure (typo) - Marek		2015-12-07 21:58:42 +01:00
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amdgpu/drm	winsys/amdgpu: addrlib - port a Fiji bug fix	2015-12-07 21:58:42 +01:00
freedreno/drm	freedreno: one screen to rule them all	2015-09-16 09:14:39 -04:00
i915/drm	gallium: replace INLINE with inline	2015-07-21 17:52:16 -04:00
intel/drm	ilo: move intel_winsys.h to core	2015-05-02 22:14:05 +08:00
nouveau/drm	nouveau: use bool instead of boolean	2015-07-21 00:42:53 +02:00
radeon	winsys/radeon: Use CPU page size instead of hardcoding 4096 bytes v3	2015-11-09 17:24:32 +09:00
svga/drm	svga: Condition preemptive flush on draw emission	2015-10-22 17:19:20 -06:00
sw	gallium/swrast: fixup build breakage and warnings	2015-10-31 16:16:44 +10:00
vc4/drm	vc4: Add support for building on Android.	2015-06-15 10:32:23 -07:00
virgl	virgl: wrap ret assignment with braces to do correct thing	2015-11-08 06:27:02 +10:00