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This is the compiler for both Bifrost and Valhall, and presumably future Mali GPUs too. Give it a more generic name so we can use the bifrost/ path for something a bit more specific. For historical reasons the compiler's name is still "bifrost" and uses the prefix `bi_`. I think that's ok in the same way that i915 in the kernel supports way more than just i915. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20455>
180 lines
7.3 KiB
Text
180 lines
7.3 KiB
Text
# Notes on opcodes
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_Notes mainly by Connor Abbott extracted from the disassembler_
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LOG_FREXPM:
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// From the ARM patent US20160364209A1:
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// "Decompose v (the input) into numbers x1 and s such that v = x1 * 2^s,
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// and x1 is a floating point value in a predetermined range where the
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// value 1 is within the range and not at one extremity of the range (e.g.
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// choose a range where 1 is towards middle of range)."
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//
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// This computes x1.
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FRCP_FREXPM:
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// Given a floating point number m * 2^e, returns m * 2^{-1}. This is
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// exactly the same as the mantissa part of frexp().
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FSQRT_FREXPM:
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// Given a floating point number m * 2^e, returns m * 2^{-2} if e is even,
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// and m * 2^{-1} if e is odd. In other words, scales by powers of 4 until
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// within the range [0.25, 1). Used for square-root and reciprocal
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// square-root.
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FRCP_FREXPE:
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// Given a floating point number m * 2^e, computes -e - 1 as an integer.
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// Zero and infinity/NaN return 0.
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FSQRT_FREXPE:
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// Computes floor(e/2) + 1.
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FRSQ_FREXPE:
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// Given a floating point number m * 2^e, computes -floor(e/2) - 1 as an
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// integer.
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LSHIFT_ADD_LOW32:
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// These instructions in the FMA slot, together with LSHIFT_ADD_HIGH32.i32
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// in the ADD slot, allow one to do a 64-bit addition with an extra small
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// shift on one of the sources. There are three possible scenarios:
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//
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// 1) Full 64-bit addition. Do:
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// out.x = LSHIFT_ADD_LOW32.i64 src1.x, src2.x, shift
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// out.y = LSHIFT_ADD_HIGH32.i32 src1.y, src2.y
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//
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// The shift amount is applied to src2 before adding. The shift amount, and
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// any extra bits from src2 plus the overflow bit, are sent directly from
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// FMA to ADD instead of being passed explicitly. Hence, these two must be
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// bundled together into the same instruction.
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//
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// 2) Add a 64-bit value src1 to a zero-extended 32-bit value src2. Do:
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// out.x = LSHIFT_ADD_LOW32.u32 src1.x, src2, shift
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// out.y = LSHIFT_ADD_HIGH32.i32 src1.x, 0
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//
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// Note that in this case, the second argument to LSHIFT_ADD_HIGH32 is
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// ignored, so it can actually be anything. As before, the shift is applied
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// to src2 before adding.
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//
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// 3) Add a 64-bit value to a sign-extended 32-bit value src2. Do:
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// out.x = LSHIFT_ADD_LOW32.i32 src1.x, src2, shift
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// out.y = LSHIFT_ADD_HIGH32.i32 src1.x, 0
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//
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// The only difference is the .i32 instead of .u32. Otherwise, this is
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// exactly the same as before.
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//
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// In all these instructions, the shift amount is stored where the third
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// source would be, so the shift has to be a small immediate from 0 to 7.
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// This is fine for the expected use-case of these instructions, which is
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// manipulating 64-bit pointers.
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//
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// These instructions can also be combined with various load/store
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// instructions which normally take a 64-bit pointer in order to add a
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// 32-bit or 64-bit offset to the pointer before doing the operation,
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// optionally shifting the offset. The load/store op implicity does
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// LSHIFT_ADD_HIGH32.i32 internally. Letting ptr be the pointer, and offset
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// the desired offset, the cases go as follows:
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//
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// 1) Add a 64-bit offset:
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// LSHIFT_ADD_LOW32.i64 ptr.x, offset.x, shift
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// ld_st_op ptr.y, offset.y, ...
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//
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// Note that the output of LSHIFT_ADD_LOW32.i64 is not used, instead being
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// implicitly sent to the load/store op to serve as the low 32 bits of the
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// pointer.
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//
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// 2) Add a 32-bit unsigned offset:
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// temp = LSHIFT_ADD_LOW32.u32 ptr.x, offset, shift
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// ld_st_op temp, ptr.y, ...
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//
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// Now, the low 32 bits of offset << shift + ptr are passed explicitly to
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// the ld_st_op, to match the case where there is no offset and ld_st_op is
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// called directly.
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//
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// 3) Add a 32-bit signed offset:
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// temp = LSHIFT_ADD_LOW32.i32 ptr.x, offset, shift
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// ld_st_op temp, ptr.y, ...
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//
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// Again, the same as the unsigned case except for the offset.
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---
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ADD ops..
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F16_TO_F32.X: // take the low 16 bits, and expand it to a 32-bit float
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F16_TO_F32.Y: // take the high 16 bits, and expand it to a 32-bit float
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MOV:
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// Logically, this should be SWZ.XY, but that's equivalent to a move, and
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// this seems to be the canonical way the blob generates a MOV.
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FRCP_FREXPM:
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// Given a floating point number m * 2^e, returns m ^ 2^{-1}.
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FLOG_FREXPE:
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// From the ARM patent US20160364209A1:
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// "Decompose v (the input) into numbers x1 and s such that v = x1 * 2^s,
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// and x1 is a floating point value in a predetermined range where the
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// value 1 is within the range and not at one extremity of the range (e.g.
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// choose a range where 1 is towards middle of range)."
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//
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// This computes s.
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LD_UBO.v4i32
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// src0 = offset, src1 = binding
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FRCP_FAST.f32:
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// *_FAST does not exist on G71 (added to G51, G72, and everything after)
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FRCP_TABLE
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// Given a floating point number m * 2^e, produces a table-based
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// approximation of 2/m using the top 17 bits. Includes special cases for
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// infinity, NaN, and zero, and copies the sign bit.
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FRCP_FAST.f16.X
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// Exists on G71
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FRSQ_TABLE:
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// A similar table for inverse square root, using the high 17 bits of the
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// mantissa as well as the low bit of the exponent.
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FRCP_APPROX:
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// Used in the argument reduction for log. Given a floating-point number
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// m * 2^e, uses the top 4 bits of m to produce an approximation to 1/m
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// with the exponent forced to 0 and only the top 5 bits are nonzero. 0,
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// infinity, and NaN all return 1.0.
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// See the ARM patent for more information.
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MUX:
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// For each bit i, return src2[i] ? src0[i] : src1[i]. In other words, this
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// is the same as (src2 & src0) | (~src2 & src1).
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ST_VAR:
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// store a varying given the address and datatype from LD_VAR_ADDR
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LD_VAR_ADDR:
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// Compute varying address and datatype (for storing in the vertex shader),
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// and store the vec3 result in the data register. The result is passed as
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// the 3 normal arguments to ST_VAR.
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DISCARD
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// Conditional discards (discard_if) in NIR. Compares the first two
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// sources and discards if the result is true
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ATEST.f32:
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// Implements alpha-to-coverage, as well as possibly the late depth and
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// stencil tests. The first source is the existing sample mask in R60
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// (possibly modified by gl_SampleMask), and the second source is the alpha
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// value. The sample mask is written right away based on the
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// alpha-to-coverage result using the normal register write mechanism,
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// since that doesn't need to read from any memory, and then written again
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// later based on the result of the stencil and depth tests using the
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// special register.
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BLEND:
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// This takes the sample coverage mask (computed by ATEST above) as a
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// regular argument, in addition to the vec4 color in the special register.
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