Lionel Landwerlin 384aaa4d3f intel: add number of subslices to device info ... We could have used a single integer to store that value, but Cannonlake has different number of subslices per slice depending on the GT. v2: Add CFL subslice numbers (Lionel) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>		2017-07-11 16:14:57 +01:00
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gen_clflush.h	intel: Fix clflushing on modern (Baytrail+) Atom CPUs.	2017-07-10 15:55:26 -07:00
gen_debug.c	i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.	2017-06-05 23:32:40 -07:00
gen_debug.h	i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.	2017-06-05 23:32:40 -07:00
gen_decoder.c	intel: gen-decoder: rework how we handle groups	2017-06-06 14:04:37 +01:00
gen_decoder.h	intel: gen-decoder: rework how we handle groups	2017-06-06 14:04:37 +01:00
gen_device_info.c	intel: add number of subslices to device info	2017-07-11 16:14:57 +01:00
gen_device_info.h	intel: add number of subslices to device info	2017-07-11 16:14:57 +01:00
gen_l3_config.c	i965/cnl: Add l3 configuration for Cannonlake	2017-06-20 12:18:26 -07:00
gen_l3_config.h	intel: Share URB configuration code between GL and Vulkan.	2016-11-19 11:40:01 -08:00
gen_sample_positions.h	intel/common: use correct header guards	2016-10-14 11:53:37 +01:00
gen_urb_config.c	i965: Fix a mistake from porting the URB allocation code to arrays.	2016-11-23 16:57:29 -08:00