Kenneth Graunke 90a2137cd5 intel/compiler: Use LSC opcode enum rather than legacy BRW_AOPs ... This gets our logical atomic messages using the lsc_opcode enum rather than the legacy BRW_AOP_* defines. We have to translate one way or another, and using the modern set makes sense going forward. One advantage is that the lsc_opcode encoding has opcodes for both integer and floating point atomics in the same enum, whereas the legacy encoding used overlapping values (BRW_AOP_AND == 1 == BRW_AOP_FMAX), which made it impossible to handle both sensibly in common code. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rohan Garg <rohan.garg@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20604>		2023-01-19 08:42:22 +00:00
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blorp	intel/blorp: Lower base_workgroup_id to zero	2023-01-18 12:21:03 +00:00
ci	ci/intel: fully utilize asus-cx9400-volteer	2023-01-19 00:44:09 +00:00
common	intel: use a shared UUID with other drivers	2023-01-17 17:36:07 +02:00
compiler	intel/compiler: Use LSC opcode enum rather than legacy BRW_AOPs	2023-01-19 08:42:22 +00:00
dev	Revert "intel/compiler: fine-grained control of dispatch widths"	2023-01-12 00:33:25 +00:00
ds	intel/utrace: document tracepoints	2023-01-13 01:22:15 +00:00
genxml	intel/genxml: Drop CACHE_MODE_SS definition.	2023-01-12 21:48:40 +00:00
isl	intel/isl: Disable CCS on MTL until B0 (Wa_14017353530)	2022-12-15 11:43:00 -08:00
nullhw-layer	utils: Merge util/debug.* into util/u_debug.* and remove util/debug.*	2022-11-02 07:25:39 +00:00
perf	intel: add MTL performance metrics	2022-12-09 09:13:02 +00:00
tools	anv,hasvk: migrate align32 to the right functions from util	2023-01-06 17:22:16 +00:00
vulkan	anv: fix generated indirect draw shader stats checks	2023-01-19 07:36:19 +00:00
vulkan_hasvk	intel/hasvk: remove some stale comments, wa was removed	2023-01-19 06:37:20 +00:00
meson.build	intel: Disable SSE2 instruction set if building for non x86 architectures	2022-11-23 16:57:23 +00:00