Ian Romanick fa74c31b22 brw: Allow additional flags registers on Xe2+ ... Xe2 adds two more flags registers. We barely use the second flags register on previous platforms, so the omission was not previously noticed. There are several efforts in progress that will add using of more flags registers. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35415>		2025-07-24 23:08:08 +00:00
..
blorp	intel: Enable CCS_E on linear surfaces on Xe2+	2025-07-21 18:36:31 +00:00
ci	iris/ci: Lower concurrency of iris-cml-traces	2025-07-14 08:15:25 +00:00
common	intel: Add INTEL_DEBUG=no-vrt	2025-07-13 21:11:02 +00:00
compiler	brw: Allow additional flags registers on Xe2+	2025-07-24 23:08:08 +00:00
decoder	intel/genxml: Remove support for start/end atttributes	2025-07-23 16:02:14 +00:00
dev	intel/dev: Add WCL PCI IDs	2025-07-21 21:22:05 +00:00
ds	intel/ds: Fix formatting of stage index.	2025-05-08 01:21:25 +00:00
executor	intel/executor: Add missing dependency to fix intermittent build failures	2025-07-07 18:35:56 +00:00
genxml	intel/genxml: Remove support for start/end atttributes	2025-07-23 16:02:14 +00:00
isl	intel: Enable CCS_E on linear surfaces on Xe2+	2025-07-21 18:36:31 +00:00
nullhw-layer	meson: include VkLayer_INTEL_nullhw in the devenv	2025-06-20 21:51:17 +00:00
perf	intel: fix monitor build dependencies	2025-06-22 10:55:21 +00:00
shaders	intel: use common CL args	2025-03-06 00:43:59 +00:00
tools	intel: fix monitor build dependencies	2025-06-22 10:55:21 +00:00
vulkan	anv: fix format compatibility check typo	2025-07-24 00:11:29 +00:00
vulkan_hasvk	anv: Remove NIR_PASS_V usage	2025-07-14 19:25:52 +00:00
meson.build	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00