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mesa/src/intel/common
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Anuj Phogat 8d02916e0c intel: Fix broxton 2x6 way size computation 
This patch is undoing the changes to way size computation
in broxton 2x6, made by below commit:

Commit: 0d576fbfbe
Author:     Anuj Phogat <anuj.phogat@gmail.com>
i965: Simplify l3 way size computations

By making use of l3_banks field in gen_device_info struct
l3_way_size for gen7+ = 2 * l3_banks.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101306
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 21:30:51 -07:00
..
gen_debug.c i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency. 2017-06-05 23:32:40 -07:00
gen_debug.h i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency. 2017-06-05 23:32:40 -07:00
gen_decoder.c intel: gen-decoder: rework how we handle groups 2017-06-06 14:04:37 +01:00
gen_decoder.h intel: gen-decoder: rework how we handle groups 2017-06-06 14:04:37 +01:00
gen_device_info.c i965: Add and initialize l3_banks field for gen7+ 2017-06-02 16:21:56 -07:00
gen_device_info.h i965: Add and initialize l3_banks field for gen7+ 2017-06-02 16:21:56 -07:00
gen_l3_config.c intel: Fix broxton 2x6 way size computation 2017-06-06 21:30:51 -07:00
gen_l3_config.h intel: Share URB configuration code between GL and Vulkan. 2016-11-19 11:40:01 -08:00
gen_sample_positions.h intel/common: use correct header guards 2016-10-14 11:53:37 +01:00
gen_urb_config.c i965: Fix a mistake from porting the URB allocation code to arrays. 2016-11-23 16:57:29 -08:00