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afdadec77f
This is a big code push. The patch is about 3000 lines.
Function isl_surf_init() calculates the physical layout of a surface.
The implementation is "complete" (but untested) for all 1D, 2D, 3D, and
cube surfaces for gen4 through gen9, except:
* gen9 1D surfaces
* gen9 Ys multisampled surfaces
* auxiliary surfaces (such as hiz, mcs, ccs)
184 lines
7.4 KiB
C
184 lines
7.4 KiB
C
/*
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* Copyright 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "isl_gen8.h"
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#include "isl_gen9.h"
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#include "isl_priv.h"
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/**
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* Calculate the LOD alignment, in units of surface samples, for the standard
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* tiling formats Yf and Ys.
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*/
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static void
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gen9_calc_std_lod_alignment_sa(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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enum isl_tiling tiling,
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enum isl_msaa_layout msaa_layout,
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struct isl_extent3d *align_sa)
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{
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const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
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assert(isl_tiling_is_std_y(tiling));
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const uint32_t bs = fmtl->bs;
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const uint32_t is_Ys = tiling == ISL_TILING_Ys;
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switch (info->dim) {
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case ISL_SURF_DIM_1D:
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/* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
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* Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
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*/
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*align_sa = (struct isl_extent3d) {
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.w = 1 << (12 - (ffs(bs) - 1) + (4 * is_Ys)),
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.h = 1,
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.d = 1,
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};
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return;
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case ISL_SURF_DIM_2D:
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/* See the Skylake BSpec > Memory Views > Common Surface Formats >
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* Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment
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* Requirements.
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*/
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*align_sa = (struct isl_extent3d) {
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.w = 1 << (6 - ((ffs(bs) - 1) / 2) + (4 * is_Ys)),
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.h = 1 << (6 - ((ffs(bs) - 0) / 2) + (4 * is_Ys)),
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.d = 1,
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};
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if (is_Ys) {
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/* FINISHME(chadv): I don't trust this code. Untested. */
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isl_finishme("%s:%s: [SKL+] multisample TileYs", __FILE__, __func__);
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switch (msaa_layout) {
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case ISL_MSAA_LAYOUT_NONE:
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case ISL_MSAA_LAYOUT_INTERLEAVED:
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break;
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case ISL_MSAA_LAYOUT_ARRAY:
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align_sa->w >>= (ffs(info->samples) - 0) / 2;
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align_sa->h >>= (ffs(info->samples) - 1) / 2;
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break;
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}
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}
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return;
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case ISL_SURF_DIM_3D:
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/* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
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* Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
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*/
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*align_sa = (struct isl_extent3d) {
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.w = 1 << (4 - ((ffs(bs) + 1) / 3) + (4 * is_Ys)),
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.h = 1 << (4 - ((ffs(bs) - 1) / 3) + (2 * is_Ys)),
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.d = 1 << (4 - ((ffs(bs) - 0) / 3) + (2 * is_Ys)),
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};
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return;
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}
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unreachable("bad isl_surface_type");
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}
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void
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gen9_choose_lod_alignment_el(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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enum isl_tiling tiling,
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enum isl_msaa_layout msaa_layout,
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struct isl_extent3d *lod_align_el)
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{
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/* This BSpec text provides some insight into the hardware's alignment
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* requirements [Skylake BSpec > Memory Views > Common Surface Formats >
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* Surface Layout and Tiling > 2D Surfaces]:
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*
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* An LOD must be aligned to a cache-line except for some special cases
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* related to Planar YUV surfaces. In general, the cache-alignment
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* restriction implies there is a minimum height for an LOD of 4 texels.
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* So, LODs which are smaller than 4 high are padded.
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*
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* From the Skylake BSpec, RENDER_SURFACE_STATE Surface Vertical Alignment:
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*
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* - For Sampling Engine and Render Target Surfaces: This field
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* specifies the vertical alignment requirement in elements for the
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* surface. [...] An element is defined as a pixel in uncompresed
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* surface formats, and as a compression block in compressed surface
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* formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
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* element is a sample.
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*
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* - This field is used for 2D, CUBE, and 3D surface alignment when Tiled
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* Resource Mode is TRMODE_NONE (Tiled Resource Mode is disabled).
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* This field is ignored for 1D surfaces and also when Tiled Resource
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* Mode is not TRMODE_NONE (e.g. Tiled Resource Mode is enabled).
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*
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* See the appropriate Alignment table in the "Surface Layout and
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* Tiling" section under Common Surface Formats for the table of
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* alignment values for Tiled Resrouces.
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*
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* - For uncompressed surfaces, the units of "j" are rows of pixels on
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* the physical surface. For compressed texture formats, the units of
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* "j" are in compression blocks, thus each increment in "j" is equal
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* to h pixels, where h is the height of the compression block in
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* pixels.
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*
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* - Valid Values: VALIGN_4, VALIGN_8, VALIGN_16
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*
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* From the Skylake BSpec, RENDER_SURFACE_STATE Surface Horizontal
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* Alignment:
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*
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* - For uncompressed surfaces, the units of "i" are pixels on the
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* physical surface. For compressed texture formats, the units of "i"
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* are in compression blocks, thus each increment in "i" is equal to
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* w pixels, where w is the width of the compression block in pixels.
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*
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* - Valid Values: HALIGN_4, HALIGN_8, HALIGN_16
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*/
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if (isl_tiling_is_std_y(tiling)) {
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struct isl_extent3d lod_align_sa;
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gen9_calc_std_lod_alignment_sa(dev, info, tiling, msaa_layout,
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&lod_align_sa);
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*lod_align_el = isl_extent3d_sa_to_el(info->format, lod_align_sa);
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return;
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}
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if (info->dim == ISL_SURF_DIM_1D) {
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/* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
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* Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
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*/
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*lod_align_el = isl_extent3d(64, 1, 1);
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return;
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}
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if (isl_format_is_compressed(info->format)) {
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/* On Gen9, the meaning of RENDER_SURFACE_STATE's
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* SurfaceHorizontalAlignment and SurfaceVerticalAlignment changed for
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* compressed formats. They now indicate a multiple of the compression
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* block. For example, if the compression mode is ETC2 then HALIGN_4
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* indicates a horizontal alignment of 16 pixels.
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*
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* To avoid wasting memory, choose the smallest alignment possible:
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* HALIGN_4 and VALIGN_4.
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*/
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*lod_align_el = isl_extent3d(4, 4, 1);
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return;
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}
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gen8_choose_lod_alignment_el(dev, info, tiling, msaa_layout, lod_align_el);
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}
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