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8b793f9567
Totals from 26026 (18.67% of 139391) affected shaders (Navi10): PreSGPRs: 370993 -> 326177 (-12.08%) Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8870>
79 lines
3.4 KiB
C++
79 lines
3.4 KiB
C++
/*
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* Copyright © 2020 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "helpers.h"
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using namespace aco;
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BEGIN_TEST(regalloc.subdword_alloc.reuse_16bit_operands)
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/* Registers of operands should be "recycled" for the output. But if the
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* input is smaller than the output, that's not generally possible. The
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* first v_cvt_f32_f16 instruction below uses the upper 16 bits of v0
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* while the lower 16 bits are still live, so the output must be stored in
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* a register other than v0. For the second v_cvt_f32_f16, the original
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* value stored in v0 is no longer used and hence it's safe to store the
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* result in v0.
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*/
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for (chip_class cc = GFX8; cc < NUM_GFX_VERSIONS; cc = (chip_class)((unsigned)cc + 1)) {
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for (bool pessimistic : { false, true }) {
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const char* subvariant = pessimistic ? "/pessimistic" : "/optimistic";
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//>> v1: %_:v[#a] = p_startpgm
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if (!setup_cs("v1", (chip_class)cc, CHIP_UNKNOWN, subvariant))
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return;
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//! v2b: %_:v[#a][0:16], v2b: %res1:v[#a][16:32] = p_split_vector %_:v[#a]
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Builder::Result tmp = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]);
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//! v1: %_:v[#b] = v_cvt_f32_f16 %_:v[#a][16:32]
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//! v1: %_:v[#a] = v_cvt_f32_f16 %_:v[#a][0:16]
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//; success = (b != a)
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auto result1 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), tmp.def(1).getTemp());
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auto result2 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), tmp.def(0).getTemp());
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writeout(0, result1);
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writeout(1, result2);
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finish_ra_test(ra_test_policy { pessimistic });
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}
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}
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END_TEST
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BEGIN_TEST(regalloc.32bit_partial_write)
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//>> v1: %_:v[0] = p_startpgm
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if (!setup_cs("v1", GFX10))
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return;
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/* ensure high 16 bits are occupied */
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//! v2b: %_:v[0][0:16], v2b: %_:v[0][16:32] = p_split_vector %_:v[0]
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Temp hi = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]).def(1).getTemp();
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/* This test checks if this instruction uses SDWA. */
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//! v2b: %_:v[0][0:16] = v_not_b32 0 dst_preserve
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Temp lo = bld.vop1(aco_opcode::v_not_b32, bld.def(v2b), Operand(0u));
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//! v1: %_:v[0] = p_create_vector %_:v[0][0:16], %_:v[0][16:32]
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bld.pseudo(aco_opcode::p_create_vector, bld.def(v1), lo, hi);
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finish_ra_test(ra_test_policy());
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END_TEST
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