mesa/src/amd
Samuel Pitoiset b968b99c45 radv: reduce radv_discard_rectangle_info::count to 8-bit
DiscardRectangleCount must be less than or equal to
maxDiscardRectangles which is limited to 4.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16778>
2022-06-01 07:59:27 +00:00
..
addrlib amd: Initialize Gfx11Lib members in constructor. 2022-05-31 03:36:53 +00:00
ci radv/ci: update the list of flakes 2022-06-01 05:26:12 +00:00
common ac/nir/taskmesh: Use 3 dimensional workgroup ID. 2022-05-31 08:24:48 +00:00
compiler aco/tests: update for GFX11's removal of SDWA 2022-05-31 18:07:34 +00:00
drm-shim Use proper types for meson objects 2022-04-18 13:03:08 +03:00
llvm ac/llvm: add use_waterfall_for_divergent_tex_samplers option 2022-05-31 13:08:07 +00:00
registers amd: change chip_class naming to "enum amd_gfx_level gfx_level" 2022-05-13 14:56:22 -04:00
vulkan radv: reduce radv_discard_rectangle_info::count to 8-bit 2022-06-01 07:59:27 +00:00
.clang-format radv: allow holes in inline push constants 2022-04-12 11:44:30 +00:00
meson.build r300/r600: Add drm-shim support. 2022-02-02 00:59:08 +00:00