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b9a359e9bd
based on notes by Dougall Johnson and Philip Turner. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
131 lines
3.7 KiB
C
131 lines
3.7 KiB
C
/*
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* Copyright 2023 Alyssa Rosenzweig
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* SPDX-License-Identifier: MIT
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*/
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#include "agx_compile.h"
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#include "agx_compiler.h"
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#include "agx_opcodes.h"
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/* Table describing the relationship between registers pressure and thread
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* count. Each entry describes a maximum number of registers and the associated
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* best-case thread count.
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*
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* Sorted in ascending order of maximum registers for easy lookup.
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*/
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static const struct agx_occupancy occupancies[] = {
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{104, 1024}, {112, 896}, {128, 832}, {136, 768}, {144, 704},
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{160, 640}, {184, 576}, {208, 512}, {232, 448}, {256, 384},
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};
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struct agx_occupancy
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agx_occupancy_for_register_count(unsigned halfregs)
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{
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for (unsigned i = 0; i < ARRAY_SIZE(occupancies); ++i) {
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unsigned max = occupancies[i].max_registers;
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assert((i == 0 || max > occupancies[i - 1].max_registers) && "ascending");
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if (halfregs <= max)
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return occupancies[i];
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}
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unreachable("Register count must be less than the maximum");
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}
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unsigned
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agx_max_registers_for_occupancy(unsigned occupancy)
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{
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unsigned max_regs = 0;
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for (unsigned i = 0; i < ARRAY_SIZE(occupancies); ++i) {
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if (occupancy <= occupancies[i].max_threads)
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max_regs = occupancies[i].max_registers;
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else
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break;
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}
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assert(max_regs > 0 && "Thread count must be less than the maximum");
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return max_regs;
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}
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/* Crude cycle model for G13G */
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enum alu_unit {
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NONE,
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SCIB,
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IC,
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F32,
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F16,
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};
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struct alu_timing {
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enum alu_unit unit;
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unsigned latency;
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unsigned tp;
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};
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/* clang-format off */
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struct alu_timing op_timings[] = {
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[AGX_OPCODE_FMA] = { F32, 2, 1 },
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[AGX_OPCODE_FADD] = { F32, 2, 1 },
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[AGX_OPCODE_FMUL] = { F32, 2, 1 },
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[AGX_OPCODE_MOV_IMM] = { SCIB, 1, 1 },
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[AGX_OPCODE_BITOP] = { SCIB, 2, 1 }, /* tp might be 2 for 32-bit / no $? */
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[AGX_OPCODE_ICMPSEL] = { SCIB, 2, 1 },
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[AGX_OPCODE_FCMPSEL] = { SCIB, 2, 1 },
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[AGX_OPCODE_IADD] = { SCIB, 2, 1 },
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[AGX_OPCODE_GET_SR] = { SCIB, 2, 2 },
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[AGX_OPCODE_GET_SR_BARRIER] = { SCIB, 2, 2 },
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[AGX_OPCODE_GET_SR_COVERAGE] = { SCIB, 2, 2 },
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[AGX_OPCODE_IMAD] = { IC, 3, 2 },
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[AGX_OPCODE_BFI] = { IC, 3, 2 },
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[AGX_OPCODE_EXTR] = { IC, 3, 2 },
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[AGX_OPCODE_ASR] = { IC, 3, 2 },
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[AGX_OPCODE_FLOOR] = { IC, 3, 2 },
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[AGX_OPCODE_SIN_PT_1] = { IC, 3, 2 },
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[AGX_OPCODE_SIN_PT_2] = { IC, 5, 2 },
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[AGX_OPCODE_LOG2] = { IC, 5, 2 },
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[AGX_OPCODE_EXP2] = { IC, 5, 2 },
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[AGX_OPCODE_RCP] = { IC, 5, 3 },
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[AGX_OPCODE_RSQRT] = { IC, 6, 4 },
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[AGX_OPCODE_SRSQRT] = { IC, 6, 4 },
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[AGX_OPCODE_SIMD_PREFIX_IADD] = { SCIB, 18, 18 },
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[AGX_OPCODE_SIMD_IADD] = { SCIB, 24, 24 },
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[AGX_OPCODE_SIMD_SHUFFLE] = { SCIB, 5, 2 },
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[AGX_OPCODE_ICMP_BALLOT] = { SCIB, 5, 2 },
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[AGX_OPCODE_FCMP_BALLOT] = { SCIB, 5, 2 },
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[AGX_OPCODE_ICMP_QUAD_BALLOT] = { SCIB, 4, 2 },
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[AGX_OPCODE_FCMP_QUAD_BALLOT] = { SCIB, 4, 2 },
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};
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/* clang-format on */
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/*
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* TODO: Model non-ALU instructions, latency, register cache, 64-bit, etc.
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*/
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struct agx_cycle_estimate
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agx_estimate_cycles(agx_context *ctx)
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{
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struct agx_cycle_estimate est = {0};
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agx_foreach_instr_global(ctx, I) {
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struct alu_timing alu = I->op < ARRAY_SIZE(op_timings)
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? op_timings[I->op]
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: (struct alu_timing){0};
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if (alu.unit == IC) {
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est.ic += alu.tp * 2;
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} else if (alu.unit) {
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est.f_scib += alu.tp;
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} else {
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/* TODO */
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}
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}
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/* IC and F/SCIB run in parallel across warps */
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est.alu = MAX2(est.ic, est.f_scib);
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return est;
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}
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