mesa/src/intel/common
Lionel Landwerlin 030abc6109 intel: compiler/i965: fix is_broxton checks
In 5f2fe9302c is_geminilake was introduced for the differenciate
broxton from geminilake. Unfortunately I failed as verifying that
is_broxton is throughout the code base to mean Gen9lp.

Fixes: 5f2fe9302c ("intel: common: add flag to identify platforms by name")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-20 23:26:42 +01:00
..
gen_debug.c i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency. 2017-06-05 23:32:40 -07:00
gen_debug.h i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency. 2017-06-05 23:32:40 -07:00
gen_decoder.c intel: gen-decoder: rework how we handle groups 2017-06-06 14:04:37 +01:00
gen_decoder.h intel: gen-decoder: rework how we handle groups 2017-06-06 14:04:37 +01:00
gen_device_info.c intel: common: add number of thread per eu 2017-06-19 22:11:00 +01:00
gen_device_info.h intel: compiler/i965: fix is_broxton checks 2017-06-20 23:26:42 +01:00
gen_l3_config.c i965/cnl: Add l3 configuration for Cannonlake 2017-06-20 12:18:26 -07:00
gen_l3_config.h intel: Share URB configuration code between GL and Vulkan. 2016-11-19 11:40:01 -08:00
gen_sample_positions.h intel/common: use correct header guards 2016-10-14 11:53:37 +01:00
gen_urb_config.c i965: Fix a mistake from porting the URB allocation code to arrays. 2016-11-23 16:57:29 -08:00