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91c28f67e6
This is to stop including nir related stuff in places that actually don't need that. Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33439>
185 lines
8.2 KiB
C
185 lines
8.2 KiB
C
/*
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* Copyright © 2017 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "ac_nir_surface.h"
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#include "ac_gpu_info.h"
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#include "nir_builder.h"
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#include "sid.h"
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static nir_def *gfx10_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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const struct gfx9_meta_equation *equation,
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int blkSizeBias, unsigned blkStart,
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nir_def *meta_pitch, nir_def *meta_slice_size,
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nir_def *x, nir_def *y, nir_def *z,
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nir_def *pipe_xor,
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nir_def **bit_position)
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{
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nir_def *zero = nir_imm_int(b, 0);
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nir_def *one = nir_imm_int(b, 1);
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assert(info->gfx_level >= GFX10);
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unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height);
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unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 + blkSizeBias;
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nir_def *coord[] = {x, y, z, 0};
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nir_def *address = zero;
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for (unsigned i = blkStart; i < blkSizeLog2 + 1; i++) {
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nir_def *v = zero;
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for (unsigned c = 0; c < 4; c++) {
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unsigned index = i * 4 + c - (blkStart * 4);
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if (equation->u.gfx10_bits[index]) {
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unsigned mask = equation->u.gfx10_bits[index];
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nir_def *bits = coord[c];
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while (mask)
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v = nir_ixor(b, v, nir_iand(b, nir_ushr_imm(b, bits, u_bit_scan(&mask)), one));
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}
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}
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address = nir_ior(b, address, nir_ishl_imm(b, v, i));
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}
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unsigned blkMask = (1 << blkSizeLog2) - 1;
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unsigned pipeMask = (1 << G_0098F8_NUM_PIPES(info->gb_addr_config)) - 1;
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unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
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nir_def *xb = nir_ushr_imm(b, x, meta_block_width_log2);
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nir_def *yb = nir_ushr_imm(b, y, meta_block_height_log2);
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nir_def *pb = nir_ushr_imm(b, meta_pitch, meta_block_width_log2);
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nir_def *blkIndex = nir_iadd(b, nir_imul(b, yb, pb), xb);
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nir_def *pipeXor = nir_iand_imm(b, nir_ishl_imm(b, nir_iand_imm(b, pipe_xor, pipeMask),
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m_pipeInterleaveLog2), blkMask);
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if (bit_position)
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*bit_position = nir_ishl_imm(b, nir_iand_imm(b, address, 1), 2);
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return nir_iadd(b, nir_iadd(b, nir_imul(b, meta_slice_size, z),
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nir_imul(b, blkIndex, nir_ishl_imm(b, one, blkSizeLog2))),
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nir_ixor(b, nir_ushr(b, address, one), pipeXor));
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}
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static nir_def *gfx9_nir_meta_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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const struct gfx9_meta_equation *equation,
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nir_def *meta_pitch, nir_def *meta_height,
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nir_def *x, nir_def *y, nir_def *z,
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nir_def *sample, nir_def *pipe_xor,
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nir_def **bit_position)
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{
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nir_def *zero = nir_imm_int(b, 0);
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nir_def *one = nir_imm_int(b, 1);
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assert(info->gfx_level >= GFX9);
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unsigned meta_block_width_log2 = util_logbase2(equation->meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(equation->meta_block_height);
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unsigned meta_block_depth_log2 = util_logbase2(equation->meta_block_depth);
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unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
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unsigned numPipeBits = equation->u.gfx9.num_pipe_bits;
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nir_def *pitchInBlock = nir_ushr_imm(b, meta_pitch, meta_block_width_log2);
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nir_def *sliceSizeInBlock = nir_imul(b, nir_ushr_imm(b, meta_height, meta_block_height_log2),
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pitchInBlock);
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nir_def *xb = nir_ushr_imm(b, x, meta_block_width_log2);
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nir_def *yb = nir_ushr_imm(b, y, meta_block_height_log2);
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nir_def *zb = nir_ushr_imm(b, z, meta_block_depth_log2);
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nir_def *blockIndex = nir_iadd(b, nir_iadd(b, nir_imul(b, zb, sliceSizeInBlock),
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nir_imul(b, yb, pitchInBlock)), xb);
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nir_def *coords[] = {x, y, z, sample, blockIndex};
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nir_def *address = zero;
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unsigned num_bits = equation->u.gfx9.num_bits;
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assert(num_bits <= 32);
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/* Compute the address up until the last bit that doesn't use the block index. */
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for (unsigned i = 0; i < num_bits - 1; i++) {
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nir_def *xor = zero;
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for (unsigned c = 0; c < 5; c++) {
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if (equation->u.gfx9.bit[i].coord[c].dim >= 5)
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continue;
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assert(equation->u.gfx9.bit[i].coord[c].ord < 32);
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nir_def *ison =
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nir_iand(b, nir_ushr_imm(b, coords[equation->u.gfx9.bit[i].coord[c].dim],
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equation->u.gfx9.bit[i].coord[c].ord), one);
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xor = nir_ixor(b, xor, ison);
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}
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address = nir_ior(b, address, nir_ishl_imm(b, xor, i));
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}
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/* Fill the remaining bits with the block index. */
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unsigned last = num_bits - 1;
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address = nir_ior(b, address,
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nir_ishl_imm(b, nir_ushr_imm(b, blockIndex,
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equation->u.gfx9.bit[last].coord[0].ord),
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last));
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if (bit_position)
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*bit_position = nir_ishl_imm(b, nir_iand_imm(b, address, 1), 2);
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nir_def *pipeXor = nir_iand_imm(b, pipe_xor, (1 << numPipeBits) - 1);
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return nir_ixor(b, nir_ushr(b, address, one),
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nir_ishl_imm(b, pipeXor, m_pipeInterleaveLog2));
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}
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nir_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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unsigned bpe, const struct gfx9_meta_equation *equation,
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nir_def *dcc_pitch, nir_def *dcc_height,
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nir_def *dcc_slice_size,
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nir_def *x, nir_def *y, nir_def *z,
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nir_def *sample, nir_def *pipe_xor)
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{
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if (info->gfx_level >= GFX10) {
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unsigned bpp_log2 = util_logbase2(bpe);
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return gfx10_nir_meta_addr_from_coord(b, info, equation, bpp_log2 - 8, 1,
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dcc_pitch, dcc_slice_size,
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x, y, z, pipe_xor, NULL);
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} else {
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return gfx9_nir_meta_addr_from_coord(b, info, equation, dcc_pitch,
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dcc_height, x, y, z,
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sample, pipe_xor, NULL);
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}
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}
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nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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const struct gfx9_meta_equation *equation,
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nir_def *cmask_pitch, nir_def *cmask_height,
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nir_def *cmask_slice_size,
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nir_def *x, nir_def *y, nir_def *z,
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nir_def *pipe_xor,
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nir_def **bit_position)
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{
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nir_def *zero = nir_imm_int(b, 0);
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if (info->gfx_level >= GFX10) {
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return gfx10_nir_meta_addr_from_coord(b, info, equation, -7, 1,
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cmask_pitch, cmask_slice_size,
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x, y, z, pipe_xor, bit_position);
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} else {
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return gfx9_nir_meta_addr_from_coord(b, info, equation, cmask_pitch,
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cmask_height, x, y, z, zero,
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pipe_xor, bit_position);
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}
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}
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nir_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info,
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const struct gfx9_meta_equation *equation,
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nir_def *htile_pitch,
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nir_def *htile_slice_size,
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nir_def *x, nir_def *y, nir_def *z,
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nir_def *pipe_xor)
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{
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return gfx10_nir_meta_addr_from_coord(b, info, equation, -4, 2,
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htile_pitch, htile_slice_size,
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x, y, z, pipe_xor, NULL);
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}
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