Kenneth Graunke 830b075e86 i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT. ... Bit 0 of the Patch Header is "TR DS Cache Disable". Setting that bit disables the DS Cache for tessellator-output topologies resulting in stitch-transition regions (but leaves it enabled for other cases). We probably shouldn't leave this to chance - the URB could contain garbage - which could result in the cache randomly being turned on or off. This patch makes the final EOT write 0 to the first DWord (which only contains this one bit). This ensures the cache is always on. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>		2016-02-09 14:54:26 -08:00
..
compiler	nir: use const_index helpers	2016-02-09 17:30:33 -05:00
egl	egl/dri2: expose srgb configs when KHR_gl_colorspace is available	2016-01-22 11:55:54 +00:00
gallium	freedreno/ir3: use const_index helpers	2016-02-09 17:30:33 -05:00
gbm	gbm.h: Add a missing stddef.h include for size_t.	2015-10-30 19:12:14 +00:00
getopt
glx	glx: update to updated version of EXT_create_context_es2_profile	2016-02-03 15:44:51 -05:00
gtest
hgl
loader	virtio_gpu: Add PCI ID to driver map	2016-01-23 12:35:24 +10:00
mapi	mesa: move GL_ARB_debug_output code into new debug_output.c file	2016-02-08 09:29:38 -07:00
mesa	i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.	2016-02-09 14:54:26 -08:00
util	util/hash_table: add _mesa_hash_table_num_entries	2016-02-03 14:03:35 +01:00
Makefile.am	glsl: move to compiler/	2016-01-26 16:08:33 +00:00
SConscript	glsl: move to compiler/	2016-01-26 16:08:33 +00:00