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1574a71438
The usual pass modernization with the twist that I don't want new drivers actually using it (-: Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Marek Olšák <maraeo@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38533>
111 lines
3.5 KiB
C
111 lines
3.5 KiB
C
/*
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* Copyright 2020 Google, Inc.
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* SPDX-License-Identifier: MIT
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*/
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#include "nir.h"
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#include "nir_builder.h"
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/*
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* A pass to split memory stores with discontinuous writemasks into multiple
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* stores with contiguous writemasks starting with .x plus address arithmetic.
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*
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* nir_lower_mem_access_bit_sizes does this (and more). Drivers that use that
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* pass should not need this one. Drivers supporting OpenCL require that pass,
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* so this one is considered deprecated and should not be used by new drivers.
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*/
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static bool
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lower(nir_builder *b, nir_intrinsic_instr *intr, void *data)
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{
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switch (intr->intrinsic) {
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_store_shared:
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case nir_intrinsic_store_global:
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case nir_intrinsic_store_scratch:
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break;
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default:
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return false;
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}
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/* if wrmask is already contiguous, then nothing to do: */
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if (nir_intrinsic_write_mask(intr) == BITFIELD_MASK(intr->num_components))
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return false;
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const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
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b->cursor = nir_before_instr(&intr->instr);
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unsigned num_srcs = info->num_srcs;
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unsigned wrmask = nir_intrinsic_write_mask(intr);
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while (wrmask) {
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unsigned first_component = ffs(wrmask) - 1;
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unsigned length = ffs(~(wrmask >> first_component)) - 1;
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nir_def *value = intr->src[0].ssa;
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/* swizzle out the consecutive components that we'll store
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* in this iteration:
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*/
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unsigned cur_mask = (BITFIELD_MASK(length) << first_component);
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value = nir_channels(b, value, cur_mask);
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/* and create the replacement intrinsic: */
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nir_intrinsic_instr *new_intr =
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nir_intrinsic_instr_create(b->shader, intr->intrinsic);
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nir_intrinsic_copy_const_indices(new_intr, intr);
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nir_intrinsic_set_write_mask(new_intr, BITFIELD_MASK(length));
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const int offset_units = value->bit_size / 8;
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if (nir_intrinsic_has_align_mul(intr)) {
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assert(nir_intrinsic_has_align_offset(intr));
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unsigned align_mul = nir_intrinsic_align_mul(intr);
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unsigned align_off = nir_intrinsic_align_offset(intr);
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align_off += offset_units * first_component;
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align_off = align_off % align_mul;
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nir_intrinsic_set_align(new_intr, align_mul, align_off);
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}
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new_intr->num_components = length;
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/* Copy the sources, replacing value, and passing everything
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* else through to the new instrution:
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*/
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for (unsigned i = 0; i < num_srcs; i++) {
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if (i == 0) {
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new_intr->src[i] = nir_src_for_ssa(value);
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} else {
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new_intr->src[i] = intr->src[i];
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}
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}
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nir_builder_instr_insert(b, &new_intr->instr);
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/* Adjust the offset. This has to be done after the new instruction has
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* been fully created and inserted, as nir_add_io_offset needs to be
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* able to inspect and rewrite sources.
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*/
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unsigned offset_adj = offset_units * first_component;
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b->cursor = nir_before_instr(&new_intr->instr);
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nir_add_io_offset(b, new_intr, offset_adj);
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/* Clear the bits in the writemask that we just wrote, then try
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* again to see if more channels are left.
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*/
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wrmask &= ~cur_mask;
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}
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/* Finally remove the original intrinsic. */
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nir_instr_remove(&intr->instr);
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return true;
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}
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bool
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nir_lower_wrmasks(nir_shader *shader)
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{
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return nir_shader_intrinsics_pass(shader, lower, nir_metadata_control_flow,
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NULL);
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}
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