Tatsuyuki Ishi 7fe469d6c8 radv: Pre-compute descriptor set layout hash. ... While analyzing cache loading performance, hashing the pipeline layout was surprisingly consuming around 4% of time, sometimes close to the cost of hashing shader modules. Turns out we were hashing the pipeline layout on every pipeline creation. Considering that pipeline layouts are usually deduplicated by the application, this was amplifying the hashing cost by a big margin. With Graphics Pipeline Library, we do need to rebuild the pipeline layout by combining those from each library, but we can memoize the hash of the descriptor set layout. The cost of re-hashing hashes is negligible since each descriptor set layout can amount to 1–2KB in size. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22254>		2023-04-03 08:46:08 +00:00
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addrlib	amd: update addrlib	2023-03-29 20:36:09 +00:00
ci	radv/ci: Update ray tracing pipeline fail/skip lists	2023-03-31 19:05:17 +00:00
common	ac/nir: add ac_nir_load_arg_at_offset	2023-04-03 01:35:06 +00:00
compiler	aco: fix nir_var_shader_out barriers for task shaders	2023-04-01 14:46:50 +00:00
drm-shim	r300: use drm_shim_override	2022-11-16 14:37:47 +00:00
llvm	ac/llvm: remove ac_build_opencoded_load_format	2023-04-03 01:35:06 +00:00
registers	amd/registers: only define SPI and COMPUTE registers in the 0xB000 range	2023-02-24 21:27:24 +00:00
vulkan	radv: Pre-compute descriptor set layout hash.	2023-04-03 08:46:08 +00:00
.clang-format	amd: Add radv_foreach_stage to ForEachMacros.	2023-03-27 08:29:35 +00:00
meson.build	meson: build radeon drm-shim also for r300 and r600	2022-11-16 14:37:47 +00:00