Samuel Pitoiset f1e339dfd6 radv: fix resetting VRS if the graphics pipeline doesn't enable it ... Otherwise the VRS state isn't reset and the graphics pipeline might still use the previous VRS state. The VRS state will only be re-emitted if it's different when the pipeline is bound. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9005 Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23052>		2023-05-17 07:51:18 +00:00
..
addrlib	amd: update addrlib	2023-03-29 20:36:09 +00:00
ci	radv/ci: document more flakes for navi21	2023-05-16 15:29:51 +00:00
common	ac: Produce unified atomic	2023-05-16 22:36:21 +00:00
compiler	aco: use c++17	2023-05-16 21:41:16 +00:00
drm-shim	amd/drm-shim: add navi10	2023-05-15 11:32:07 +00:00
llvm	ac/llvm: remove redundant nir_lower_legacy_atomics	2023-05-16 04:10:32 +00:00
registers	amd/registers: use gfx9 packet definitions for gfx940	2023-04-06 15:00:54 +00:00
vulkan	radv: fix resetting VRS if the graphics pipeline doesn't enable it	2023-05-17 07:51:18 +00:00
.clang-format	amd: Add radv_foreach_stage to ForEachMacros.	2023-03-27 08:29:35 +00:00
meson.build	meson: build radeonsi with aco	2023-05-15 02:01:10 +00:00