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d0669f3ede
Update existing workarounds when necessary to match changed identifiers. Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23226>
146 lines
4.8 KiB
C
146 lines
4.8 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef INTEL_GENX_STATE_H
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#define INTEL_GENX_STATE_H
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#ifndef GFX_VERx10
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#error This file should only be included by genX files.
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#endif
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#include <stdbool.h>
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#include "dev/intel_device_info.h"
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#include "genxml/gen_macros.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if GFX_VER >= 7
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static inline void
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intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
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const struct intel_device_info *devinfo,
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const struct brw_wm_prog_data *prog_data,
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unsigned rasterization_samples,
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enum brw_wm_msaa_flags msaa_flags)
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{
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assert(rasterization_samples != 0);
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bool enable_8 = prog_data->dispatch_8;
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bool enable_16 = prog_data->dispatch_16;
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bool enable_32 = prog_data->dispatch_32;
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#if GFX_VER >= 9
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/* SKL PRMs, Volume 2a: Command Reference: Instructions:
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* 3DSTATE_PS_BODY::8 Pixel Dispatch Enable:
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*
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* "When Render Target Fast Clear Enable is ENABLED or Render Target
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* Resolve Type = RESOLVE_PARTIAL or RESOLVE_FULL, this bit must be
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* DISABLED."
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*/
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if (ps->RenderTargetFastClearEnable ||
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ps->RenderTargetResolveType == RESOLVE_PARTIAL ||
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ps->RenderTargetResolveType == RESOLVE_FULL)
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enable_8 = false;
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#elif GFX_VER >= 8
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/* BDW has the same wording as SKL, except some of the fields mentioned
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* don't exist...
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*/
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if (ps->RenderTargetFastClearEnable ||
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ps->RenderTargetResolveEnable)
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enable_8 = false;
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#endif
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const bool is_persample_dispatch =
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brw_wm_prog_data_is_persample(prog_data, msaa_flags);
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if (is_persample_dispatch) {
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/* TGL PRMs, Volume 2d: Command Reference: Structures:
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* 3DSTATE_PS_BODY::32 Pixel Dispatch Enable:
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*
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* "Must not be enabled when dispatch rate is sample AND NUM_MULTISAMPLES > 1."
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*/
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if (GFX_VER >= 12 && rasterization_samples > 1)
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enable_32 = false;
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/* Starting with SandyBridge (where we first get MSAA), the different
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* pixel dispatch combinations are grouped into classifications A
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* through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware
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* generations, the only configurations supporting persample dispatch
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* are those in which only one dispatch width is enabled.
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*
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* The Gfx12 hardware spec has a similar dispatch grouping table, but
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* the following conflicting restriction applies (from the page on
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* "Structure_3DSTATE_PS_BODY"), so we need to keep the SIMD16 shader:
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*
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* "SIMD32 may only be enabled if SIMD16 or (dual)SIMD8 is also
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* enabled."
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*/
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if (enable_32 || enable_16)
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enable_8 = false;
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if (GFX_VER < 12 && enable_32)
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enable_16 = false;
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}
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/* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
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*
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* "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
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* SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
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* mode."
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*
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* 16x MSAA only exists on Gfx9+, so we can skip this on Gfx8.
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*/
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if (GFX_VER >= 9 && rasterization_samples == 16 && !is_persample_dispatch) {
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assert(enable_8 || enable_16);
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enable_32 = false;
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}
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assert(enable_8 || enable_16 || enable_32);
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ps->_8PixelDispatchEnable = enable_8;
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ps->_16PixelDispatchEnable = enable_16;
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ps->_32PixelDispatchEnable = enable_32;
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}
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#endif
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#if GFX_VERx10 >= 125
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UNUSED static int
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preferred_slm_allocation_size(const struct intel_device_info *devinfo)
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{
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if (intel_needs_workaround(devinfo, 14017245111))
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return SLM_ENCODES_96K;
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return 0;
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* INTEL_GENX_STATE_H */
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