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887642b0f2
Add support for disabling the VRT (Variable Register Thread) feature. The strategy here is to force the old BRW_MAX_GRF limit for the register allocator (locks the upper limit) and make sure ptl_register_blocks() always return that amount of blocks (locks the lower limit). Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35781>
398 lines
14 KiB
C
398 lines
14 KiB
C
/*
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* Copyright © 2015-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_compiler.h"
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#include "brw_eu.h"
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#include "brw_nir.h"
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#include "brw_private.h"
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#include "dev/intel_debug.h"
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#include "compiler/nir/nir.h"
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#include "isl/isl.h"
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#include "util/u_debug.h"
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const struct nir_shader_compiler_options brw_scalar_nir_options = {
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.avoid_ternary_with_two_constants = true,
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.compact_arrays = true,
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.discard_is_demote = true,
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.divergence_analysis_options =
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(nir_divergence_single_patch_per_tcs_subgroup |
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nir_divergence_single_patch_per_tes_subgroup |
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nir_divergence_shader_record_ptr_uniform),
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.force_indirect_unrolling = nir_var_function_temp,
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.has_bfe = true,
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.has_bfi = true,
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.has_bfm = true,
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.has_pack_32_4x8 = true,
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.has_uclz = true,
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.lower_base_vertex = true,
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.lower_bitfield_extract = true,
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.lower_bitfield_extract8 = true,
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.lower_bitfield_extract16 = true,
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.lower_bitfield_insert = true,
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.lower_device_index_to_zero = true,
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.lower_fdiv = true,
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.lower_fisnormal = true,
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.lower_flrp16 = true,
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.lower_flrp64 = true,
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.lower_fmod = true,
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.lower_fquantize2f16 = true,
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.lower_hadd64 = true,
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.lower_insert_byte = true,
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.lower_insert_word = true,
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.lower_isign = true,
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.lower_ldexp = true,
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.lower_pack_half_2x16 = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_snorm_4x8 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_pack_unorm_4x8 = true,
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.lower_pack_64_4x16 = true,
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.lower_scmp = true,
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.lower_to_scalar = true,
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.lower_uadd_carry = true,
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.lower_ufind_msb = true,
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.lower_uniforms_to_ubo = true,
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.lower_unpack_half_2x16 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_snorm_4x8 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_unpack_unorm_4x8 = true,
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.lower_usub_borrow = true,
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.max_unroll_iterations = 32,
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.support_16bit_alu = true,
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.vectorize_tess_levels = true,
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.vertex_id_zero_based = true,
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.scalarize_ddx = true,
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.support_indirect_inputs = BITFIELD_BIT(PIPE_SHADER_TESS_CTRL) |
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BITFIELD_BIT(PIPE_SHADER_TESS_EVAL) |
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BITFIELD_BIT(PIPE_SHADER_FRAGMENT),
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.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
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.per_view_unique_driver_locations = true,
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.compact_view_index = true,
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};
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struct brw_compiler *
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brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
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{
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struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
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assert(devinfo->ver >= 9);
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compiler->devinfo = devinfo;
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brw_init_isa_info(&compiler->isa, devinfo);
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brw_alloc_reg_sets(compiler);
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compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false);
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compiler->use_tcs_multi_patch = devinfo->ver >= 12;
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compiler->indirect_ubos_use_sampler = devinfo->ver < 12;
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compiler->lower_dpas = !devinfo->has_systolic ||
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debug_get_bool_option("INTEL_LOWER_DPAS", false);
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nir_lower_int64_options int64_options =
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nir_lower_imul64 |
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nir_lower_isign64 |
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nir_lower_divmod64 |
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nir_lower_imul_high64 |
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nir_lower_find_lsb64 |
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nir_lower_ufind_msb64 |
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nir_lower_bit_count64 |
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nir_lower_iadd3_64 |
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nir_lower_bitfield_extract64 |
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nir_lower_bitfield_reverse64;
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nir_lower_doubles_options fp64_options =
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nir_lower_drcp |
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nir_lower_dsqrt |
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nir_lower_drsq |
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nir_lower_dsign |
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nir_lower_dtrunc |
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nir_lower_dfloor |
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nir_lower_dceil |
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nir_lower_dfract |
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nir_lower_dround_even |
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nir_lower_dmod |
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nir_lower_dsub |
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nir_lower_ddiv;
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if (!devinfo->has_64bit_float || INTEL_DEBUG(DEBUG_SOFT64))
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fp64_options |= nir_lower_fp64_full_software;
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if (!devinfo->has_64bit_int)
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int64_options |= (nir_lower_int64_options)~0;
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/* The Bspec's section titled "Instruction_multiply[DevBDW+]" claims that
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* destination type can be Quadword and source type Doubleword for Gfx8 and
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* Gfx9. So, lower 64 bit multiply instruction on rest of the platforms.
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*/
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if (devinfo->ver > 9)
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int64_options |= nir_lower_imul_2x32_64;
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if (devinfo->ver >= 20)
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int64_options |= (nir_lower_icmp64 | nir_lower_minmax64 |
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nir_lower_logic64 | nir_lower_ufind_msb64 |
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nir_lower_bit_count64 |
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nir_lower_bcsel64 |
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nir_lower_extract64 | nir_lower_scan_reduce_bitwise64 |
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nir_lower_scan_reduce_iadd64 | nir_lower_subgroup_shuffle64 |
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nir_lower_iadd_sat64 | nir_lower_uadd_sat64);
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/* We want the GLSL compiler to emit code that uses condition codes */
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for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
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struct nir_shader_compiler_options *nir_options =
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rzalloc(compiler, struct nir_shader_compiler_options);
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*nir_options = brw_scalar_nir_options;
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int64_options |= nir_lower_usub_sat64;
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/* Gfx11 loses LRP. */
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nir_options->lower_flrp32 = devinfo->ver >= 11;
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nir_options->lower_fpow = devinfo->ver >= 12;
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nir_options->has_rotate16 = devinfo->ver >= 11;
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nir_options->has_rotate32 = devinfo->ver >= 11;
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nir_options->has_iadd3 = devinfo->verx10 >= 125;
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nir_options->has_sdot_4x8 = devinfo->ver >= 12;
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nir_options->has_udot_4x8 = devinfo->ver >= 12;
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nir_options->has_sudot_4x8 = devinfo->ver >= 12;
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nir_options->has_sdot_4x8_sat = devinfo->ver >= 12;
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nir_options->has_udot_4x8_sat = devinfo->ver >= 12;
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nir_options->has_sudot_4x8_sat = devinfo->ver >= 12;
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nir_options->lower_int64_options = int64_options;
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nir_options->lower_doubles_options = fp64_options;
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nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
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nir_options->force_indirect_unrolling |=
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brw_nir_no_indirect_mask(compiler, i);
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if (compiler->use_tcs_multi_patch) {
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/* TCS MULTI_PATCH mode has multiple patches per subgroup */
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nir_options->divergence_analysis_options &=
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~nir_divergence_single_patch_per_tcs_subgroup;
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}
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if (devinfo->ver < 12)
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nir_options->divergence_analysis_options |=
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nir_divergence_single_prim_per_subgroup;
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compiler->nir_options[i] = nir_options;
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}
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/* Build a list of storage format compatible in component bit size &
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* isl_base_type. We can apply the same lowering to those.
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*/
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compiler->num_lowered_storage_formats = 0;
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for (enum isl_format fmt = 0; fmt < ISL_FORMAT_RAW; fmt++) {
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if (!isl_is_storage_image_format(devinfo, fmt))
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continue;
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if (isl_lower_storage_image_format(devinfo, fmt) == fmt)
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continue;
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compiler->lowered_storage_formats =
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reralloc(compiler, compiler->lowered_storage_formats,
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uint32_t, compiler->num_lowered_storage_formats + 1);
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compiler->lowered_storage_formats[
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compiler->num_lowered_storage_formats++] = fmt;
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}
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assert((devinfo->verx10 >= 125 &&
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compiler->num_lowered_storage_formats == 0) ||
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(devinfo->verx10 >= 110 && devinfo->verx10 <= 120 &&
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compiler->num_lowered_storage_formats == 3) ||
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devinfo->verx10 == 90);
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return compiler;
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}
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static void
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insert_u64_bit(uint64_t *val, bool add)
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{
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*val = (*val << 1) | !!add;
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}
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uint64_t
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brw_get_compiler_config_value(const struct brw_compiler *compiler)
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{
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uint64_t config = 0;
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unsigned bits = 0;
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insert_u64_bit(&config, compiler->precise_trig);
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bits++;
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insert_u64_bit(&config, compiler->lower_dpas);
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bits++;
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enum intel_debug_flag debug_bits[] = {
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DEBUG_NO_DUAL_OBJECT_GS,
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DEBUG_SPILL_FS,
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DEBUG_SPILL_VEC4,
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DEBUG_NO_COMPACTION,
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DEBUG_DO32,
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DEBUG_SOFT64,
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DEBUG_NO_SEND_GATHER,
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DEBUG_NO_VRT,
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};
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for (uint32_t i = 0; i < ARRAY_SIZE(debug_bits); i++) {
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insert_u64_bit(&config, INTEL_DEBUG(debug_bits[i]));
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bits++;
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}
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uint64_t mask = SIMD_DISK_CACHE_MASK;
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bits += util_bitcount64(mask);
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u_foreach_bit64(bit, mask)
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insert_u64_bit(&config, (intel_simd & (1ULL << bit)) != 0);
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mask = 3;
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bits += util_bitcount64(mask);
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assert(bits <= util_bitcount64(UINT64_MAX));
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return config;
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}
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void
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brw_device_sha1(char *hex,
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const struct intel_device_info *devinfo) {
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struct mesa_sha1 ctx;
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_mesa_sha1_init(&ctx);
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brw_device_sha1_update(&ctx, devinfo);
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unsigned char result[20];
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_mesa_sha1_final(&ctx, result);
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_mesa_sha1_format(hex, result);
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}
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unsigned
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brw_prog_data_size(gl_shader_stage stage)
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{
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static const size_t stage_sizes[] = {
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[MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_data),
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[MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_data),
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[MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_data),
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[MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_data),
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[MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_data),
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[MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_data),
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[MESA_SHADER_TASK] = sizeof(struct brw_task_prog_data),
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[MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_data),
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[MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_data),
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[MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_data),
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[MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_data),
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[MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_data),
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[MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_data),
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[MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_data),
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[MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_data),
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};
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assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
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return stage_sizes[stage];
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}
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unsigned
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brw_prog_key_size(gl_shader_stage stage)
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{
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static const size_t stage_sizes[] = {
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[MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_key),
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[MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_key),
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[MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_key),
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[MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_key),
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[MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_key),
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[MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_key),
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[MESA_SHADER_TASK] = sizeof(struct brw_task_prog_key),
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[MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_key),
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[MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_key),
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[MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_key),
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[MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_key),
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[MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_key),
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[MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_key),
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[MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_key),
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[MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_key),
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};
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assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
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return stage_sizes[stage];
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}
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void
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brw_write_shader_relocs(const struct brw_isa_info *isa,
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void *program,
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const struct brw_stage_prog_data *prog_data,
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struct brw_shader_reloc_value *values,
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unsigned num_values)
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{
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for (unsigned i = 0; i < prog_data->num_relocs; i++) {
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assert(prog_data->relocs[i].offset % 8 == 0);
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void *dst = program + prog_data->relocs[i].offset;
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for (unsigned j = 0; j < num_values; j++) {
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if (prog_data->relocs[i].id == values[j].id) {
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uint32_t value = values[j].value + prog_data->relocs[i].delta;
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switch (prog_data->relocs[i].type) {
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case BRW_SHADER_RELOC_TYPE_U32:
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*(uint32_t *)dst = value;
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break;
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case BRW_SHADER_RELOC_TYPE_MOV_IMM:
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brw_update_reloc_imm(isa, dst, value);
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break;
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default:
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unreachable("Invalid relocation type");
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}
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break;
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}
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}
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}
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}
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void
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brw_stage_prog_data_add_printf(struct brw_stage_prog_data *prog_data,
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void *mem_ctx,
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const u_printf_info *print)
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{
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prog_data->printf_info_count++;
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prog_data->printf_info = reralloc(mem_ctx, prog_data->printf_info,
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u_printf_info,
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prog_data->printf_info_count);
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prog_data->printf_info[prog_data->printf_info_count - 1] = *print;
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if (print->string_size > 0) {
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prog_data->printf_info[prog_data->printf_info_count - 1].strings =
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ralloc_size(mem_ctx, print->string_size);
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memcpy(prog_data->printf_info[prog_data->printf_info_count - 1].strings,
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print->strings, print->string_size);
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}
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if (print->num_args > 0) {
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prog_data->printf_info[prog_data->printf_info_count - 1].arg_sizes =
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ralloc_array(mem_ctx, __typeof__(*print->arg_sizes), print->num_args);
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memcpy(prog_data->printf_info[prog_data->printf_info_count - 1].arg_sizes,
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print->arg_sizes, sizeof(print->arg_sizes[0]) *print->num_args);
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}
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}
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unsigned
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ptl_register_blocks(unsigned grf_used)
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{
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if (INTEL_DEBUG(DEBUG_NO_VRT))
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return (BRW_MAX_GRF / 32) - 1;
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const unsigned n = DIV_ROUND_UP(grf_used, 32) - 1;
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return (n < 6 ? n : 7);
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}
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