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c8852719d0
To match other helpers. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29192>
255 lines
9.6 KiB
C
255 lines
9.6 KiB
C
/*
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* Copyright © 2021 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#include <inttypes.h>
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#include "radv_buffer.h"
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#include "radv_cs.h"
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#include "radv_spm.h"
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#include "sid.h"
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#define SPM_RING_BASE_ALIGN 32
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static bool
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radv_spm_init_bo(struct radv_device *device)
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{
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struct radeon_winsys *ws = device->ws;
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uint64_t size = 32 * 1024 * 1024; /* Default to 1MB. */
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uint16_t sample_interval = 4096; /* Default to 4096 clk. */
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VkResult result;
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device->spm.buffer_size = size;
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device->spm.sample_interval = sample_interval;
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struct radeon_winsys_bo *bo = NULL;
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result = radv_bo_create(device, NULL, size, 4096, RADEON_DOMAIN_VRAM,
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_ZERO_VRAM,
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RADV_BO_PRIORITY_SCRATCH, 0, true, &bo);
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device->spm.bo = bo;
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if (result != VK_SUCCESS)
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return false;
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result = ws->buffer_make_resident(ws, device->spm.bo, true);
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if (result != VK_SUCCESS)
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return false;
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device->spm.ptr = radv_buffer_map(ws, device->spm.bo);
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if (!device->spm.ptr)
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return false;
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return true;
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}
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static void
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radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf)
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const enum amd_gfx_level gfx_level = pdev->info.gfx_level;
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struct ac_spm *spm = &device->spm;
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if (gfx_level >= GFX11) {
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for (uint32_t instance = 0; instance < ARRAY_SIZE(spm->sq_wgp); instance++) {
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uint32_t num_counters = spm->sq_wgp[instance].num_counters;
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if (!num_counters)
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continue;
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radeon_check_space(device->ws, cs, 3 + num_counters * 3);
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radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, spm->sq_wgp[instance].grbm_gfx_index);
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for (uint32_t b = 0; b < num_counters; b++) {
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const struct ac_spm_counter_select *cntr_sel = &spm->sq_wgp[instance].counters[b];
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uint32_t reg_base = R_036700_SQ_PERFCOUNTER0_SELECT;
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radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg_base + b * 4, 1);
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radeon_emit(cs, cntr_sel->sel0);
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}
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}
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}
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for (uint32_t instance = 0; instance < ARRAY_SIZE(spm->sqg); instance++) {
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uint32_t num_counters = spm->sqg[instance].num_counters;
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if (!num_counters)
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continue;
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radeon_check_space(device->ws, cs, 3 + num_counters * 3);
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radeon_set_uconfig_reg(
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cs, R_030800_GRBM_GFX_INDEX,
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S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1) | S_030800_SE_INDEX(instance));
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for (uint32_t b = 0; b < num_counters; b++) {
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const struct ac_spm_counter_select *cntr_sel = &spm->sqg[instance].counters[b];
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uint32_t reg_base = R_036700_SQ_PERFCOUNTER0_SELECT;
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radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, reg_base + b * 4, 1);
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radeon_emit(cs, cntr_sel->sel0 | S_036700_SQC_BANK_MASK(0xf)); /* SQC_BANK_MASK only gfx10 */
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}
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}
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for (uint32_t b = 0; b < spm->num_block_sel; b++) {
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struct ac_spm_block_select *block_sel = &spm->block_sel[b];
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struct ac_pc_block_base *regs = block_sel->b->b->b;
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for (unsigned i = 0; i < block_sel->num_instances; i++) {
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struct ac_spm_block_instance *block_instance = &block_sel->instances[i];
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radeon_check_space(device->ws, cs, 3 + (AC_SPM_MAX_COUNTER_PER_BLOCK * 6));
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radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, block_instance->grbm_gfx_index);
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for (unsigned c = 0; c < block_instance->num_counters; c++) {
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const struct ac_spm_counter_select *cntr_sel = &block_instance->counters[c];
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if (!cntr_sel->active)
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continue;
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radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, regs->select0[c], 1);
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radeon_emit(cs, cntr_sel->sel0);
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radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, regs->select1[c], 1);
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radeon_emit(cs, cntr_sel->sel1);
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}
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}
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}
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/* Restore global broadcasting. */
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radeon_set_uconfig_reg(
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cs, R_030800_GRBM_GFX_INDEX,
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S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1));
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}
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void
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radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs, enum radv_queue_family qf)
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const enum amd_gfx_level gfx_level = pdev->info.gfx_level;
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struct ac_spm *spm = &device->spm;
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uint64_t va = radv_buffer_get_va(spm->bo);
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uint64_t ring_size = spm->buffer_size;
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/* It's required that the ring VA and the size are correctly aligned. */
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assert(!(va & (SPM_RING_BASE_ALIGN - 1)));
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assert(!(ring_size & (SPM_RING_BASE_ALIGN - 1)));
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assert(spm->sample_interval >= 32);
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radeon_check_space(device->ws, cs, 27);
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/* Configure the SPM ring buffer. */
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radeon_set_uconfig_reg(cs, R_037200_RLC_SPM_PERFMON_CNTL,
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S_037200_PERFMON_RING_MODE(0) | /* no stall and no interrupt on overflow */
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S_037200_PERFMON_SAMPLE_INTERVAL(spm->sample_interval)); /* in sclk */
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radeon_set_uconfig_reg(cs, R_037204_RLC_SPM_PERFMON_RING_BASE_LO, va);
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radeon_set_uconfig_reg(cs, R_037208_RLC_SPM_PERFMON_RING_BASE_HI, S_037208_RING_BASE_HI(va >> 32));
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radeon_set_uconfig_reg(cs, R_03720C_RLC_SPM_PERFMON_RING_SIZE, ring_size);
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/* Configure the muxsel. */
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uint32_t total_muxsel_lines = 0;
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for (unsigned s = 0; s < AC_SPM_SEGMENT_TYPE_COUNT; s++) {
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total_muxsel_lines += spm->num_muxsel_lines[s];
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}
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radeon_set_uconfig_reg(cs, R_03726C_RLC_SPM_ACCUM_MODE, 0);
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if (pdev->info.gfx_level >= GFX11) {
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radeon_set_uconfig_reg(cs, R_03721C_RLC_SPM_PERFMON_SEGMENT_SIZE,
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S_03721C_TOTAL_NUM_SEGMENT(total_muxsel_lines) |
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S_03721C_GLOBAL_NUM_SEGMENT(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_GLOBAL]) |
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S_03721C_SE_NUM_SEGMENT(spm->max_se_muxsel_lines));
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radeon_set_uconfig_reg(cs, R_037210_RLC_SPM_RING_WRPTR, 0);
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} else {
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radeon_set_uconfig_reg(cs, R_037210_RLC_SPM_PERFMON_SEGMENT_SIZE, 0);
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radeon_set_uconfig_reg(cs, R_03727C_RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE,
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S_03727C_SE0_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_SE0]) |
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S_03727C_SE1_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_SE1]) |
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S_03727C_SE2_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_SE2]) |
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S_03727C_SE3_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_SE3]));
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radeon_set_uconfig_reg(cs, R_037280_RLC_SPM_PERFMON_GLB_SEGMENT_SIZE,
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S_037280_PERFMON_SEGMENT_SIZE(total_muxsel_lines) |
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S_037280_GLOBAL_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_GLOBAL]));
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}
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/* Upload each muxsel ram to the RLC. */
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for (unsigned s = 0; s < AC_SPM_SEGMENT_TYPE_COUNT; s++) {
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unsigned rlc_muxsel_addr, rlc_muxsel_data;
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unsigned grbm_gfx_index = S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1);
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if (!spm->num_muxsel_lines[s])
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continue;
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if (s == AC_SPM_SEGMENT_TYPE_GLOBAL) {
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grbm_gfx_index |= S_030800_SE_BROADCAST_WRITES(1);
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rlc_muxsel_addr =
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gfx_level >= GFX11 ? R_037220_RLC_SPM_GLOBAL_MUXSEL_ADDR : R_037224_RLC_SPM_GLOBAL_MUXSEL_ADDR;
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rlc_muxsel_data =
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gfx_level >= GFX11 ? R_037224_RLC_SPM_GLOBAL_MUXSEL_DATA : R_037228_RLC_SPM_GLOBAL_MUXSEL_DATA;
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} else {
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grbm_gfx_index |= S_030800_SE_INDEX(s);
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rlc_muxsel_addr = gfx_level >= GFX11 ? R_037228_RLC_SPM_SE_MUXSEL_ADDR : R_03721C_RLC_SPM_SE_MUXSEL_ADDR;
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rlc_muxsel_data = gfx_level >= GFX11 ? R_03722C_RLC_SPM_SE_MUXSEL_DATA : R_037220_RLC_SPM_SE_MUXSEL_DATA;
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}
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radeon_check_space(device->ws, cs, 3 + spm->num_muxsel_lines[s] * (7 + AC_SPM_MUXSEL_LINE_SIZE));
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radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, grbm_gfx_index);
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for (unsigned l = 0; l < spm->num_muxsel_lines[s]; l++) {
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uint32_t *data = (uint32_t *)spm->muxsel_lines[s][l].muxsel;
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/* Select MUXSEL_ADDR to point to the next muxsel. */
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radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, rlc_muxsel_addr, l * AC_SPM_MUXSEL_LINE_SIZE);
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/* Write the muxsel line configuration with MUXSEL_DATA. */
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + AC_SPM_MUXSEL_LINE_SIZE, 0));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEM_MAPPED_REGISTER) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME) |
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S_370_WR_ONE_ADDR(1));
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radeon_emit(cs, rlc_muxsel_data >> 2);
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radeon_emit(cs, 0);
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radeon_emit_array(cs, data, AC_SPM_MUXSEL_LINE_SIZE);
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}
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}
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/* Select SPM counters. */
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radv_emit_spm_counters(device, cs, qf);
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}
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bool
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radv_spm_init(struct radv_device *device)
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{
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struct radv_physical_device *pdev = radv_device_physical(device);
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const struct radeon_info *gpu_info = &pdev->info;
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struct ac_perfcounters *pc = &pdev->ac_perfcounters;
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/* We failed to initialize the performance counters. */
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if (!pc->blocks)
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return false;
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if (!ac_init_spm(gpu_info, pc, &device->spm))
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return false;
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if (!radv_spm_init_bo(device))
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return false;
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return true;
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}
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void
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radv_spm_finish(struct radv_device *device)
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{
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struct radeon_winsys *ws = device->ws;
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if (device->spm.bo) {
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ws->buffer_make_resident(ws, device->spm.bo, false);
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radv_bo_destroy(device, NULL, device->spm.bo);
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}
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ac_destroy_spm(&device->spm);
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}
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