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5cc36887ab
This changes the pass to extract pinned instructions and not just unpinned instructions when rescheduling instructions. This stops pinned instructions from being bunched together when instructions are reinserted into the blocks which can result in regressions with regards to cycles and instruction counts on i965 and register use/Max Waves on AMD hardware. In order to do this we also throw away the post-order depth-first search linearization algorithm used to re-insert the instructions, which itself causes possible regressions when instructions are reinserted into a less than ideal new order (of which the bunched together pinned instructions is one example). Instead we simply insert instructions in the reverse order they were extracted. This will simply place instructions that were scheduled earlier onto the end of their new block and instructions that were scheduled later to the start of their new block. With this everything should remain in order without the need to run over uses. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/597> |
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| glsl | ||
| nir | ||
| spirv | ||
| builtin_type_macros.h | ||
| glsl_types.cpp | ||
| glsl_types.h | ||
| meson.build | ||
| nir_types.cpp | ||
| nir_types.h | ||
| shader_enums.c | ||
| shader_enums.h | ||
| shader_info.h | ||