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335 lines
13 KiB
C
335 lines
13 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "gen7_pack.h"
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#include "gen75_pack.h"
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GENX_FUNC(GEN7, GEN75) void
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genX(fill_buffer_surface_state)(void *state, const struct anv_format *format,
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uint32_t offset, uint32_t range,
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uint32_t stride)
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{
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uint32_t num_elements = range / stride;
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struct GENX(RENDER_SURFACE_STATE) surface_state = {
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.SurfaceType = SURFTYPE_BUFFER,
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.SurfaceFormat = format->surface_format,
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.SurfaceVerticalAlignment = VALIGN_4,
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.SurfaceHorizontalAlignment = HALIGN_4,
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.TiledSurface = false,
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.RenderCacheReadWriteMode = false,
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.SurfaceObjectControlState = GENX(MOCS),
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.Height = (num_elements >> 7) & 0x3fff,
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.Width = num_elements & 0x7f,
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.Depth = (num_elements >> 21) & 0x3f,
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.SurfacePitch = stride - 1,
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# if (ANV_IS_HASWELL)
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.ShaderChannelSelectR = SCS_RED,
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.ShaderChannelSelectG = SCS_GREEN,
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.ShaderChannelSelectB = SCS_BLUE,
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.ShaderChannelSelectA = SCS_ALPHA,
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# endif
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.SurfaceBaseAddress = { NULL, offset },
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};
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GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
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}
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static const uint32_t vk_to_gen_tex_filter[] = {
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[VK_FILTER_NEAREST] = MAPFILTER_NEAREST,
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[VK_FILTER_LINEAR] = MAPFILTER_LINEAR
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};
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static const uint32_t vk_to_gen_mipmap_mode[] = {
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[VK_SAMPLER_MIPMAP_MODE_BASE] = MIPFILTER_NONE,
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[VK_SAMPLER_MIPMAP_MODE_NEAREST] = MIPFILTER_NEAREST,
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[VK_SAMPLER_MIPMAP_MODE_LINEAR] = MIPFILTER_LINEAR
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};
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static const uint32_t vk_to_gen_tex_address[] = {
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[VK_SAMPLER_ADDRESS_MODE_REPEAT] = TCM_WRAP,
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[VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
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[VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE] = TCM_CLAMP,
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[VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
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[VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
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};
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static const uint32_t vk_to_gen_compare_op[] = {
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[VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
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[VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
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[VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
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[VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
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[VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
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[VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
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[VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
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[VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
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};
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static struct anv_state
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alloc_surface_state(struct anv_device *device,
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struct anv_cmd_buffer *cmd_buffer)
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{
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if (cmd_buffer) {
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return anv_cmd_buffer_alloc_surface_state(cmd_buffer);
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} else {
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return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
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}
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}
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VkResult genX(CreateSampler)(
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VkDevice _device,
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const VkSamplerCreateInfo* pCreateInfo,
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const VkAllocationCallbacks* pAllocator,
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VkSampler* pSampler)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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struct anv_sampler *sampler;
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uint32_t mag_filter, min_filter, max_anisotropy;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
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sampler = anv_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (!sampler)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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if (pCreateInfo->maxAnisotropy > 1) {
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mag_filter = MAPFILTER_ANISOTROPIC;
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min_filter = MAPFILTER_ANISOTROPIC;
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max_anisotropy = (pCreateInfo->maxAnisotropy - 2) / 2;
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} else {
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mag_filter = vk_to_gen_tex_filter[pCreateInfo->magFilter];
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min_filter = vk_to_gen_tex_filter[pCreateInfo->minFilter];
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max_anisotropy = RATIO21;
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}
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struct GEN7_SAMPLER_STATE sampler_state = {
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.SamplerDisable = false,
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.TextureBorderColorMode = DX10OGL,
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.BaseMipLevel = 0.0,
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.MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode],
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.MagModeFilter = mag_filter,
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.MinModeFilter = min_filter,
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.TextureLODBias = pCreateInfo->mipLodBias * 256,
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.AnisotropicAlgorithm = EWAApproximation,
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.MinLOD = pCreateInfo->minLod,
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.MaxLOD = pCreateInfo->maxLod,
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.ChromaKeyEnable = 0,
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.ChromaKeyIndex = 0,
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.ChromaKeyMode = 0,
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.ShadowFunction = vk_to_gen_compare_op[pCreateInfo->compareOp],
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.CubeSurfaceControlMode = 0,
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.BorderColorPointer =
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device->border_colors.offset +
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pCreateInfo->borderColor * sizeof(float) * 4,
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.MaximumAnisotropy = max_anisotropy,
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.RAddressMinFilterRoundingEnable = 0,
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.RAddressMagFilterRoundingEnable = 0,
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.VAddressMinFilterRoundingEnable = 0,
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.VAddressMagFilterRoundingEnable = 0,
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.UAddressMinFilterRoundingEnable = 0,
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.UAddressMagFilterRoundingEnable = 0,
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.TrilinearFilterQuality = 0,
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.NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
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.TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
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.TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
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.TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
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};
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GEN7_SAMPLER_STATE_pack(NULL, sampler->state, &sampler_state);
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*pSampler = anv_sampler_to_handle(sampler);
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return VK_SUCCESS;
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}
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static const uint8_t anv_halign[] = {
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[4] = HALIGN_4,
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[8] = HALIGN_8,
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};
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static const uint8_t anv_valign[] = {
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[2] = VALIGN_2,
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[4] = VALIGN_4,
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};
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static const uint32_t vk_to_gen_swizzle_map[] = {
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[VK_COMPONENT_SWIZZLE_ZERO] = SCS_ZERO,
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[VK_COMPONENT_SWIZZLE_ONE] = SCS_ONE,
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[VK_COMPONENT_SWIZZLE_R] = SCS_RED,
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[VK_COMPONENT_SWIZZLE_G] = SCS_GREEN,
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[VK_COMPONENT_SWIZZLE_B] = SCS_BLUE,
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[VK_COMPONENT_SWIZZLE_A] = SCS_ALPHA
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};
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static inline uint32_t
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vk_to_gen_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component)
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{
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if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
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return vk_to_gen_swizzle_map[component];
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else
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return vk_to_gen_swizzle_map[swizzle];
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}
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GENX_FUNC(GEN7, GEN75) void
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genX(image_view_init)(struct anv_image_view *iview,
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struct anv_device *device,
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const VkImageViewCreateInfo* pCreateInfo,
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struct anv_cmd_buffer *cmd_buffer)
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{
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ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
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const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
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struct anv_surface *surface =
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anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
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const struct anv_format *format =
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anv_format_for_vk_format(pCreateInfo->format);
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if (pCreateInfo->viewType != VK_IMAGE_VIEW_TYPE_2D)
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anv_finishme("non-2D image views");
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iview->image = image;
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iview->bo = image->bo;
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iview->offset = image->offset + surface->offset;
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iview->format = anv_format_for_vk_format(pCreateInfo->format);
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iview->extent = (VkExtent3D) {
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.width = anv_minify(image->extent.width, range->baseMipLevel),
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.height = anv_minify(image->extent.height, range->baseMipLevel),
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.depth = anv_minify(image->extent.depth, range->baseMipLevel),
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};
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uint32_t depth = 1;
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if (range->layerCount > 1) {
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depth = range->layerCount;
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} else if (image->extent.depth > 1) {
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depth = image->extent.depth;
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}
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const struct isl_extent3d lod_align_sa =
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isl_surf_get_lod_alignment_sa(&surface->isl);
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struct GENX(RENDER_SURFACE_STATE) surface_state = {
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.SurfaceType = image->surface_type,
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.SurfaceArray = image->array_size > 1,
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.SurfaceFormat = format->surface_format,
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.SurfaceVerticalAlignment = anv_valign[lod_align_sa.height],
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.SurfaceHorizontalAlignment = anv_halign[lod_align_sa.width],
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/* From bspec (DevSNB, DevIVB): "Set Tile Walk to TILEWALK_XMAJOR if
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* Tiled Surface is False."
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*/
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.TiledSurface = surface->isl.tiling != ISL_TILING_LINEAR,
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.TileWalk = surface->isl.tiling == ISL_TILING_Y0 ?
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TILEWALK_YMAJOR : TILEWALK_XMAJOR,
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.VerticalLineStride = 0,
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.VerticalLineStrideOffset = 0,
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.RenderCacheReadWriteMode = 0, /* TEMPLATE */
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.Height = image->extent.height - 1,
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.Width = image->extent.width - 1,
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.Depth = depth - 1,
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.SurfacePitch = surface->isl.row_pitch - 1,
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.MinimumArrayElement = range->baseArrayLayer,
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.NumberofMultisamples = MULTISAMPLECOUNT_1,
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.XOffset = 0,
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.YOffset = 0,
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.SurfaceObjectControlState = GENX(MOCS),
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.MIPCountLOD = 0, /* TEMPLATE */
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.SurfaceMinLOD = 0, /* TEMPLATE */
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.MCSEnable = false,
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# if (ANV_IS_HASWELL)
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.ShaderChannelSelectR = vk_to_gen_swizzle(pCreateInfo->components.r,
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VK_COMPONENT_SWIZZLE_R),
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.ShaderChannelSelectG = vk_to_gen_swizzle(pCreateInfo->components.g,
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VK_COMPONENT_SWIZZLE_G),
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.ShaderChannelSelectB = vk_to_gen_swizzle(pCreateInfo->components.b,
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VK_COMPONENT_SWIZZLE_B),
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.ShaderChannelSelectA = vk_to_gen_swizzle(pCreateInfo->components.a,
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VK_COMPONENT_SWIZZLE_A),
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# else /* XXX: Seriously? */
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.RedClearColor = 0,
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.GreenClearColor = 0,
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.BlueClearColor = 0,
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.AlphaClearColor = 0,
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# endif
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.ResourceMinLOD = 0.0,
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.SurfaceBaseAddress = { NULL, iview->offset },
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};
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if (image->needs_nonrt_surface_state) {
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iview->nonrt_surface_state = alloc_surface_state(device, cmd_buffer);
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surface_state.RenderCacheReadWriteMode = false;
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/* For non render target surfaces, the hardware interprets field
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* MIPCount/LOD as MIPCount. The range of levels accessible by the
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* sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
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*/
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surface_state.SurfaceMinLOD = range->baseMipLevel;
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surface_state.MIPCountLOD = range->levelCount - 1;
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GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->nonrt_surface_state.map,
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&surface_state);
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if (!device->info.has_llc)
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anv_state_clflush(iview->nonrt_surface_state);
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}
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if (image->needs_color_rt_surface_state) {
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iview->color_rt_surface_state = alloc_surface_state(device, cmd_buffer);
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surface_state.RenderCacheReadWriteMode = 0; /* Write only */
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/* For render target surfaces, the hardware interprets field MIPCount/LOD as
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* LOD. The Broadwell PRM says:
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*
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* MIPCountLOD defines the LOD that will be rendered into.
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* SurfaceMinLOD is ignored.
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*/
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surface_state.MIPCountLOD = range->baseMipLevel;
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surface_state.SurfaceMinLOD = 0;
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GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->color_rt_surface_state.map,
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&surface_state);
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if (!device->info.has_llc)
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anv_state_clflush(iview->color_rt_surface_state);
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}
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}
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