Bas Nieuwenhuizen 76daa30e4a radv: Use correct flush bits for flushing L2 during CB/DB flushes. ... Copied from radeonsi. Putting in the correct metadata flush commands for eventually not flushing L2 on CB/DB switch. Does not remove the need for V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT at the moment. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>		2018-01-04 19:35:36 +01:00
..
addrlib	amd: remove always-true BRAHMA_BUILD define	2017-12-01 13:49:42 +00:00
common	amd/common: scan if gl_PrimitiveID is used before translating to LLVM	2018-01-04 18:43:09 +01:00
vulkan	radv: Use correct flush bits for flushing L2 during CB/DB flushes.	2018-01-04 19:35:36 +01:00
Android.addrlib.mk	amd: remove always-true BRAHMA_BUILD define	2017-12-01 13:49:42 +00:00
Android.common.mk	Android: fix undeclared identifier 'gfx9d_reg_table'	2017-09-11 09:35:23 -05:00
Android.mk	android: amd/common: add support for libmesa_amd_common	2016-11-05 18:42:29 +01:00
Makefile.addrlib.am	amd: remove always-true BRAHMA_BUILD define	2017-12-01 13:49:42 +00:00
Makefile.am	ac: automake: rework sid_tables.h generation	2017-01-12 19:29:28 +00:00
Makefile.common.am	ac/common: always build NIR translation	2017-07-31 17:59:10 +02:00
Makefile.sources	amd/common: add ac_get_spi_shader_z_format()	2017-12-14 22:23:23 +01:00
meson.build	meson: build "radv" vulkan driver for radeon hardware	2017-09-27 09:12:34 -07:00