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f3272f0044
They will be also used for per-submit captures. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32370>
125 lines
4.6 KiB
C
125 lines
4.6 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_SQTT_H
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#define RADV_SQTT_H
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#include "radv_device.h"
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struct radv_cmd_buffer;
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struct radv_dispatch_info;
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struct radv_graphics_pipeline;
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struct radv_barrier_data {
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union {
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struct {
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uint16_t depth_stencil_expand : 1;
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uint16_t htile_hiz_range_expand : 1;
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uint16_t depth_stencil_resummarize : 1;
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uint16_t dcc_decompress : 1;
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uint16_t fmask_decompress : 1;
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uint16_t fast_clear_eliminate : 1;
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uint16_t fmask_color_expand : 1;
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uint16_t init_mask_ram : 1;
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uint16_t reserved : 8;
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};
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uint16_t all;
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} layout_transitions;
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};
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/**
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* Value for the reason field of an RGP barrier start marker originating from
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* the Vulkan client (does not include PAL-defined values). (Table 15)
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*/
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enum rgp_barrier_reason {
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RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF,
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/* External app-generated barrier reasons, i.e. API synchronization
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* commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
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*/
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RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001,
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RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002,
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RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003,
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/* Internal barrier reasons, i.e. implicit synchronization inserted by
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* the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
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*/
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RGP_BARRIER_INTERNAL_BASE = 0xC0000000,
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RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0,
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RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1,
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RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2,
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RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3
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};
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bool radv_is_instruction_timing_enabled(void);
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bool radv_sqtt_queue_events_enabled(void);
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void radv_emit_sqtt_userdata(const struct radv_cmd_buffer *cmd_buffer, const void *data, uint32_t num_dwords);
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void radv_emit_spi_config_cntl(const struct radv_device *device, struct radeon_cmdbuf *cs, bool enable);
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void radv_emit_inhibit_clockgating(const struct radv_device *device, struct radeon_cmdbuf *cs, bool inhibit);
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VkResult radv_sqtt_acquire_gpu_timestamp(struct radv_device *device, struct radeon_winsys_bo **gpu_timestamp_bo,
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uint32_t *gpu_timestamp_offset, void **gpu_timestamp_ptr);
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bool radv_sqtt_init(struct radv_device *device);
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void radv_sqtt_finish(struct radv_device *device);
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void radv_sqtt_start_capturing(struct radv_queue *queue);
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bool radv_sqtt_stop_capturing(struct radv_queue *queue);
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bool radv_get_sqtt_trace(struct radv_queue *queue, struct ac_sqtt_trace *sqtt_trace);
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void radv_reset_sqtt_trace(struct radv_device *device);
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bool radv_sqtt_sample_clocks(struct radv_device *device);
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VkResult radv_sqtt_get_timed_cmdbuf(struct radv_queue *queue, struct radeon_winsys_bo *timestamp_bo,
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uint32_t timestamp_offset, VkPipelineStageFlags2 timestamp_stage,
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VkCommandBuffer *pcmdbuf);
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void radv_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv_graphics_pipeline *pipeline);
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void radv_write_user_event_marker(struct radv_cmd_buffer *cmd_buffer, enum rgp_sqtt_marker_user_event_type type,
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const char *str);
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void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
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void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
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void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
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void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info);
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void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer, VkImageAspectFlagBits aspects);
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void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
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void radv_describe_begin_render_pass_resolve(struct radv_cmd_buffer *cmd_buffer);
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void radv_describe_end_render_pass_resolve(struct radv_cmd_buffer *cmd_buffer);
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void radv_describe_barrier_end_delayed(struct radv_cmd_buffer *cmd_buffer);
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void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer, enum rgp_barrier_reason reason);
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void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer);
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void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer, const struct radv_barrier_data *barrier);
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void radv_describe_begin_accel_struct_build(struct radv_cmd_buffer *cmd_buffer, uint32_t count);
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void radv_describe_end_accel_struct_build(struct radv_cmd_buffer *cmd_buffer);
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#endif /* RADV_SQTT_H */
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