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Before: 30453 ./build/src/intel/genxml/gen125_pack.h After: 17026 ./build/src/intel/genxml/gen125_pack.h 21589 ./build/src/intel/genxml/gen125_video_pack.h The idea is to have fewer line to parse in each genX_*.c file. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
23 lines
756 B
C
23 lines
756 B
C
/* Copyright © 2024 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#pragma once
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/* We reserve :
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* - GPR 13 for STATE_BASE_ADDRESS bindless surface base address
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* - GPR 14 for perf queries
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* - GPR 15 for conditional rendering
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*/
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#define MI_BUILDER_NUM_ALLOC_GPRS 13
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#ifndef MI_BUILDER_CAN_WRITE_BATCH
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#define MI_BUILDER_CAN_WRITE_BATCH true
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#endif
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/* Don't do any write check by default, we manually set it where it matters.
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*/
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#define MI_BUILDER_DEFAULT_WRITE_CHECK false
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#define __gen_get_batch_dwords anv_batch_emit_dwords
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#define __gen_address_offset anv_address_add
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#define __gen_get_batch_address(b, a) anv_batch_address(b, a)
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#define __gen_get_write_fencing_status(b) (&(b)->write_fence_status)
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#include "common/mi_builder.h"
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