mesa/src/virtio
Yiwei Zhang c6187962a2 venus: workaround cacheline overflush issue on Intel JSL
We observed that Venus on ANV on JSL platform has some cacheline flush
issue. The overflush shows up as:
1. There're 2 threads venus bliting the feedback buffers suballocated
   from the same backing device memory, back to back.
2. On thread A, flushing the feedback buffer for cpu read is placed
   behind flushing a shader storage buffer for cpu read.
3. On thread B, flushing a different feedback buffer with the same
   backing device memory (different offset bound to) can kick the
   feedback buffer flush in (2) earlier than it should be flushed.
4. As a result, CPU polling thread for thread B results would see venus
   feedback buffer update earlier than shader storage buffer results
   being updated, breaking Venus sync primitives optimization.

During investigation, a solid workaround for JSL platform is to force
Venus to align up to 128 bytes for feedback buffer suballocation while
the default is at 64 bytes.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30879>
(cherry picked from commit 7941d705c3)
2024-08-28 15:31:32 +02:00
..
ci venus/ci: skip timing out test 2024-07-21 14:42:58 +02:00
vdrm format: Generate endian-independent format aliases 2024-07-19 13:50:42 +00:00
venus-protocol venus: sync headers for VK_EXT_external_memory_acquire_unmodified 2024-07-10 18:57:26 +00:00
virtio-gpu virgl: Update headers 2024-05-23 20:02:03 +00:00
vtest venus: rename sync_queue -> timeline 2022-12-16 21:12:38 +00:00
vulkan venus: workaround cacheline overflush issue on Intel JSL 2024-08-28 15:31:32 +02:00
meson.build build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00