Qiang Yu 73ea7d651a ac/llvm: nir_load_smem_amd support 32bit base address ... For radeonsi which use 32bit address in ac_build_load_to_sgpr(). Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>		2022-12-02 07:34:31 +00:00
..
clc	clc: add 32-bit target	2022-10-15 02:23:03 +00:00
glsl	meson: do not use source_root() when possible	2022-11-22 06:11:07 +00:00
isaspec	isaspec: Move isa_decode(..) declaration	2022-09-03 19:26:04 +00:00
nir	ac/llvm: nir_load_smem_amd support 32bit base address	2022-12-02 07:34:31 +00:00
spirv	nir/builder: Drop nir_i2i and nir_u2u in favor of nir_x2xN	2022-12-01 01:10:12 +00:00
builtin_type_macros.h	glsl: add texture subpass variants	2022-11-10 10:21:34 +00:00
glsl_types.cpp	glsl: add texture subpass variants	2022-11-10 10:21:34 +00:00
glsl_types.h	glsl: Remove the need of _MTX_INITIALIZER_NP by using simple_mtx_t/SIMPLE_MTX_INITIALIZER	2022-11-09 04:38:28 +00:00
meson.build	spirv: Use a single binary for gtests	2021-10-20 17:55:36 +00:00
nir_gl_types.h	mesa: #include "util/glheader.h" instead GL/gl.h in shared code	2022-11-03 16:07:31 +00:00
nir_types.cpp	nir/types: Add some asserts to glsl_get_struct_field()	2022-11-01 14:48:41 +00:00
nir_types.h	nir: Add a pass to lower mediump temps and shared mem.	2022-09-01 22:39:39 +00:00
shader_enums.c	nir+ir3: Rename load_size_ir3 to load_center_rhw_ir3.	2022-07-11 16:56:05 +00:00
shader_enums.h	gallium: use gl shader types as the basis for the gallium ones	2022-08-04 08:17:39 +00:00
shader_info.h	nir, anv, hasvk, radv: pull uses_wide_subgroup_intrinsics into shader_info	2022-09-20 10:19:21 +00:00