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21636ff9fa
The hope here is to replace our backend handling for loading whole
cachelines at a time from UBOs into NIR-based handling, which plays
nicely with the NIR load/store vectorizer.
Rounding down offsets to multiples of 64B allows us to globally CSE
UBO loads across basic blocks. This is really useful. However, blindly
rounding down the offset to a multiple of 64B can trigger anti-patterns
where...a single unaligned memory load could have hit all the necessary
data, but rounding it down split it into two loads.
By moving this to NIR, we gain more control of the interplay between
nir_opt_load_store_vectorize and this rebasing and CSE'ing. The backend
can then simply load between nir_def_{first,last}_component_read() and
trust that our NIR has the loads blockified appropriately.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32888>
47 lines
1.5 KiB
C
47 lines
1.5 KiB
C
/*
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* Copyright (c) 2015-2023 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#pragma once
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#include "nir.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct intel_device_info;
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void intel_nir_apply_tcs_quads_workaround(nir_shader *nir);
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bool brw_nir_rebase_const_offset_ubo_loads(nir_shader *shader);
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bool intel_nir_blockify_uniform_loads(nir_shader *shader,
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const struct intel_device_info *devinfo);
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bool intel_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader);
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bool intel_nir_clamp_per_vertex_loads(nir_shader *shader);
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bool intel_nir_cleanup_resource_intel(nir_shader *shader);
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bool intel_nir_lower_conversions(nir_shader *nir);
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bool intel_nir_lower_non_uniform_barycentric_at_sample(nir_shader *nir);
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bool intel_nir_lower_non_uniform_resource_intel(nir_shader *shader);
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bool intel_nir_lower_patch_vertices_in(nir_shader *shader, unsigned input_vertices);
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bool intel_nir_lower_shading_rate_output(nir_shader *nir);
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bool intel_nir_lower_sparse_intrinsics(nir_shader *nir);
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struct intel_nir_lower_texture_opts {
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bool combined_lod_and_array_index;
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bool combined_lod_or_bias_and_offset;
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};
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bool intel_nir_lower_texture(nir_shader *nir,
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const struct intel_nir_lower_texture_opts *opts);
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bool intel_nir_opt_peephole_ffma(nir_shader *shader);
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bool intel_nir_opt_peephole_imul32x16(nir_shader *shader);
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bool intel_nir_pulls_at_sample(nir_shader *shader);
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bool intel_nir_lower_printf(nir_shader *nir);
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#ifdef __cplusplus
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}
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#endif
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