mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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cf3bb77224
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32536>
730 lines
23 KiB
C++
730 lines
23 KiB
C++
/*
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* Copyright © 2010 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include "brw_shader.h"
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#include "brw_builder.h"
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#include "util/half_float.h"
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static uint64_t
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src_as_uint(const brw_reg &src)
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{
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assert(src.file == IMM);
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switch (src.type) {
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case BRW_TYPE_W:
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return (uint64_t)(int16_t)(src.ud & 0xffff);
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case BRW_TYPE_UW:
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return (uint64_t)(uint16_t)(src.ud & 0xffff);
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case BRW_TYPE_D:
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return (uint64_t)src.d;
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case BRW_TYPE_UD:
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return (uint64_t)src.ud;
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case BRW_TYPE_Q:
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return src.d64;
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case BRW_TYPE_UQ:
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return src.u64;
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default:
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unreachable("Invalid integer type.");
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}
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}
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static double
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src_as_float(const brw_reg &src)
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{
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assert(src.file == IMM);
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switch (src.type) {
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case BRW_TYPE_HF:
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return _mesa_half_to_float((uint16_t)src.d);
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case BRW_TYPE_F:
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return src.f;
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case BRW_TYPE_DF:
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return src.df;
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default:
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unreachable("Invalid float type.");
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}
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}
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static brw_reg
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brw_imm_for_type(uint64_t value, enum brw_reg_type type)
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{
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switch (type) {
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case BRW_TYPE_W:
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return brw_imm_w(value);
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case BRW_TYPE_UW:
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return brw_imm_uw(value);
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case BRW_TYPE_D:
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return brw_imm_d(value);
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case BRW_TYPE_UD:
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return brw_imm_ud(value);
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case BRW_TYPE_Q:
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return brw_imm_d(value);
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case BRW_TYPE_UQ:
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return brw_imm_uq(value);
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default:
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unreachable("Invalid integer type.");
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}
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}
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/**
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* Converts a MAD to an ADD by folding the multiplicand sources.
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*/
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static void
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fold_multiplicands_of_MAD(brw_inst *inst)
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{
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assert(inst->opcode == BRW_OPCODE_MAD);
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assert (inst->src[1].file == IMM &&
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inst->src[2].file == IMM &&
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!brw_type_is_vector_imm(inst->src[1].type) &&
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!brw_type_is_vector_imm(inst->src[2].type));
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if (brw_type_is_int(inst->src[1].type)) {
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const uint64_t imm1 = src_as_uint(inst->src[1]);
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const uint64_t imm2 = src_as_uint(inst->src[2]);
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brw_reg product = brw_imm_ud(imm1 * imm2);
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inst->src[1] = retype(product,
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brw_type_larger_of(inst->src[1].type,
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inst->src[2].type));
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} else {
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const double product = src_as_float(inst->src[1]) *
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src_as_float(inst->src[2]);
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switch (brw_type_larger_of(inst->src[1].type,
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inst->src[2].type)) {
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case BRW_TYPE_HF:
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inst->src[1] = retype(brw_imm_w(_mesa_float_to_half(product)),
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BRW_TYPE_HF);
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break;
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case BRW_TYPE_F:
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inst->src[1] = brw_imm_f(product);
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break;
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case BRW_TYPE_DF:
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unreachable("float64 should be impossible.");
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break;
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default:
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unreachable("Invalid float type.");
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}
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}
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inst->opcode = BRW_OPCODE_ADD;
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inst->resize_sources(2);
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}
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bool
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brw_opt_constant_fold_instruction(const intel_device_info *devinfo, brw_inst *inst)
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{
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bool progress = false;
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switch (inst->opcode) {
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case BRW_OPCODE_ADD:
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if (inst->src[0].file != IMM || inst->src[1].file != IMM)
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break;
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if (brw_type_is_int(inst->src[0].type)) {
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const uint64_t src0 = src_as_uint(inst->src[0]);
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const uint64_t src1 = src_as_uint(inst->src[1]);
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inst->src[0] = brw_imm_for_type(src0 + src1, inst->dst.type);
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} else {
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assert(inst->src[0].type == BRW_TYPE_F);
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inst->src[0].f += inst->src[1].f;
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}
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inst->opcode = BRW_OPCODE_MOV;
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inst->resize_sources(1);
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progress = true;
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break;
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case BRW_OPCODE_ADD3:
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if (inst->src[0].file == IMM &&
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inst->src[1].file == IMM &&
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inst->src[2].file == IMM) {
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const uint64_t src0 = src_as_uint(inst->src[0]);
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const uint64_t src1 = src_as_uint(inst->src[1]);
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const uint64_t src2 = src_as_uint(inst->src[2]);
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inst->opcode = BRW_OPCODE_MOV;
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inst->src[0] = brw_imm_for_type(src0 + src1 + src2,
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inst->dst.type);
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inst->resize_sources(1);
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progress = true;
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}
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break;
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case BRW_OPCODE_AND:
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if (inst->src[0].file == IMM && inst->src[1].file == IMM) {
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const uint64_t src0 = src_as_uint(inst->src[0]);
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const uint64_t src1 = src_as_uint(inst->src[1]);
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inst->opcode = BRW_OPCODE_MOV;
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inst->src[0] = brw_imm_for_type(src0 & src1, inst->dst.type);
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inst->resize_sources(1);
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progress = true;
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break;
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}
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break;
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case BRW_OPCODE_MAD:
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if (inst->src[1].file == IMM &&
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inst->src[2].file == IMM &&
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inst->src[3].file == IMM &&
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!brw_type_is_vector_imm(inst->src[1].type) &&
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!brw_type_is_vector_imm(inst->src[2].type) &&
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!brw_type_is_vector_imm(inst->src[3].type)) {
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fold_multiplicands_of_MAD(inst);
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assert(inst->opcode == BRW_OPCODE_ADD);
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ASSERTED bool folded = brw_opt_constant_fold_instruction(devinfo, inst);
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assert(folded);
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progress = true;
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break;
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}
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break;
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case BRW_OPCODE_MUL:
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if (brw_type_is_float(inst->src[1].type))
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break;
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/* From the BDW PRM, Vol 2a, "mul - Multiply":
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*
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* "When multiplying integer datatypes, if src0 is DW and src1
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* is W, irrespective of the destination datatype, the
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* accumulator maintains full 48-bit precision."
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* ...
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* "When multiplying integer data types, if one of the sources
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* is a DW, the resulting full precision data is stored in
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* the accumulator."
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*
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* There are also similar notes in earlier PRMs.
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*
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* The MOV instruction can copy the bits of the source, but it
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* does not clear the higher bits of the accumulator. So, because
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* we might use the full accumulator in the MUL/MACH macro, we
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* shouldn't replace such MULs with MOVs.
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*/
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if ((brw_type_size_bytes(inst->src[0].type) == 4 ||
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brw_type_size_bytes(inst->src[1].type) == 4) &&
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(inst->dst.is_accumulator() ||
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inst->writes_accumulator_implicitly(devinfo)))
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break;
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if (inst->src[0].is_zero() || inst->src[1].is_zero()) {
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inst->opcode = BRW_OPCODE_MOV;
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inst->src[0] = brw_imm_d(0);
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inst->resize_sources(1);
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progress = true;
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break;
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}
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if (inst->src[0].file == IMM && inst->src[1].file == IMM) {
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const uint64_t src0 = src_as_uint(inst->src[0]);
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const uint64_t src1 = src_as_uint(inst->src[1]);
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inst->opcode = BRW_OPCODE_MOV;
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inst->src[0] = brw_imm_for_type(src0 * src1, inst->dst.type);
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inst->resize_sources(1);
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progress = true;
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break;
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}
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break;
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case BRW_OPCODE_OR:
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if (inst->src[0].file == IMM && inst->src[1].file == IMM) {
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const uint64_t src0 = src_as_uint(inst->src[0]);
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const uint64_t src1 = src_as_uint(inst->src[1]);
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inst->opcode = BRW_OPCODE_MOV;
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inst->src[0] = brw_imm_for_type(src0 | src1, inst->dst.type);
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inst->resize_sources(1);
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progress = true;
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break;
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}
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break;
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case BRW_OPCODE_SHL:
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if (inst->src[0].file == IMM && inst->src[1].file == IMM) {
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/* It's not currently possible to generate this, and this constant
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* folding does not handle it.
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*/
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assert(!inst->saturate);
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brw_reg result;
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switch (brw_type_size_bytes(inst->src[0].type)) {
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case 2:
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result = brw_imm_uw(0x0ffff & (inst->src[0].ud << (inst->src[1].ud & 0x1f)));
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break;
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case 4:
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result = brw_imm_ud(inst->src[0].ud << (inst->src[1].ud & 0x1f));
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break;
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case 8:
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result = brw_imm_uq(inst->src[0].u64 << (inst->src[1].ud & 0x3f));
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break;
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default:
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/* Just in case a future platform re-enables B or UB types. */
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unreachable("Invalid source size.");
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}
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inst->opcode = BRW_OPCODE_MOV;
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inst->src[0] = retype(result, inst->dst.type);
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inst->resize_sources(1);
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progress = true;
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}
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break;
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default:
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break;
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}
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#ifndef NDEBUG
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/* The function is only intended to do constant folding, so the result of
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* progress must be a MOV of an immediate value.
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*/
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if (progress) {
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assert(inst->opcode == BRW_OPCODE_MOV);
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assert(inst->src[0].file == IMM);
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}
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#endif
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return progress;
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}
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bool
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brw_opt_algebraic(brw_shader &s)
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{
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const intel_device_info *devinfo = s.devinfo;
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bool progress = false;
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foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) {
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if (brw_opt_constant_fold_instruction(devinfo, inst)) {
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progress = true;
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continue;
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}
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switch (inst->opcode) {
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case BRW_OPCODE_ADD:
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if (brw_type_is_int(inst->src[1].type) &&
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inst->src[1].is_zero()) {
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inst->opcode = BRW_OPCODE_MOV;
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inst->resize_sources(1);
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progress = true;
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}
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break;
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case BRW_OPCODE_ADD3: {
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const unsigned num_imm = (inst->src[0].file == IMM) +
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(inst->src[1].file == IMM) +
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(inst->src[2].file == IMM);
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/* If there is more than one immediate value, fold the values and
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* convert the instruction to either ADD or MOV.
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*/
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assert(num_imm < 3);
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if (num_imm == 2) {
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uint64_t sum = 0;
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brw_reg src;
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for (unsigned i = 0; i < 3; i++) {
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if (inst->src[i].file == IMM) {
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sum += src_as_uint(inst->src[i]);
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} else {
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assert(src.file == BAD_FILE);
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src = inst->src[i];
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}
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}
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assert(src.file != BAD_FILE);
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if (uint32_t(sum) == 0) {
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inst->opcode = BRW_OPCODE_MOV;
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inst->src[0] = src;
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inst->resize_sources(1);
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} else {
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inst->opcode = BRW_OPCODE_ADD;
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inst->src[0] = src;
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inst->src[1] = brw_imm_ud(sum);
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inst->resize_sources(2);
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}
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progress = true;
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} else if (num_imm == 1) {
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/* If there is a single constant, and that constant is zero,
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* convert the instruction to regular ADD.
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*/
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for (unsigned i = 0; i < 3; i++) {
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if (inst->src[i].is_zero()) {
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inst->opcode = BRW_OPCODE_ADD;
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inst->src[i] = inst->src[2];
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inst->resize_sources(2);
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progress = true;
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break;
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}
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}
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}
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break;
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}
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case BRW_OPCODE_MOV:
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if ((inst->conditional_mod == BRW_CONDITIONAL_Z ||
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inst->conditional_mod == BRW_CONDITIONAL_NZ) &&
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inst->dst.is_null() &&
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(inst->src[0].abs || inst->src[0].negate)) {
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inst->src[0].abs = false;
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inst->src[0].negate = false;
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progress = true;
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break;
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}
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if (inst->src[0].file != IMM)
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break;
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if (inst->saturate) {
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/* Full mixed-type saturates don't happen. However, we can end up
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* with things like:
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*
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* mov.sat(8) g21<1>DF -1F
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*
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* Other mixed-size-but-same-base-type cases may also be possible.
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*/
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if (inst->dst.type != inst->src[0].type &&
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inst->dst.type != BRW_TYPE_DF &&
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inst->src[0].type != BRW_TYPE_F)
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assert(!"unimplemented: saturate mixed types");
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if (brw_reg_saturate_immediate(&inst->src[0])) {
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inst->saturate = false;
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progress = true;
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}
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}
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break;
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case BRW_OPCODE_MUL:
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if (brw_type_is_int(inst->src[0].type)){
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/* From the BDW PRM, Vol 2a, "mul - Multiply":
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*
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* "When multiplying integer datatypes, if src0 is DW and src1
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* is W, irrespective of the destination datatype, the
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* accumulator maintains full 48-bit precision."
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* ...
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* "When multiplying integer data types, if one of the sources
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* is a DW, the resulting full precision data is stored in the
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* accumulator."
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*
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* There are also similar notes in earlier PRMs.
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*
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* The MOV instruction can copy the bits of the source, but it
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* does not clear the higher bits of the accumulator. So, because
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* we might use the full accumulator in the MUL/MACH macro, we
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* shouldn't replace such MULs with MOVs.
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*/
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if ((brw_type_size_bytes(inst->src[0].type) == 4 ||
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brw_type_size_bytes(inst->src[1].type) == 4) &&
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(inst->dst.is_accumulator() ||
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inst->writes_accumulator_implicitly(devinfo)))
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break;
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for (unsigned i = 0; i < 2; i++) {
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/* a * 1 = a */
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if (inst->src[i].is_one()) {
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inst->opcode = BRW_OPCODE_MOV;
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} else if (inst->src[i].is_negative_one()) {
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/* a * -1 = -a */
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inst->opcode = BRW_OPCODE_MOV;
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/* If the source other than the -1 is immediate, just
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* toggling the negation flag will not work. Due to the
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* previous call to brw_constant_fold_instruction, this
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* should not be possible.
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*/
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assert(inst->src[1 - i].file != IMM);
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inst->src[1 - i].negate = !inst->src[1 - i].negate;
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}
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if (inst->opcode == BRW_OPCODE_MOV) {
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/* If the literal 1 was src0, put the old src1 in src0. */
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if (i == 0)
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inst->src[0] = inst->src[1];
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inst->resize_sources(1);
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progress = true;
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break;
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}
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}
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}
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break;
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case BRW_OPCODE_OR:
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if (inst->src[0].equals(inst->src[1]) || inst->src[1].is_zero()) {
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/* On Gfx8+, the OR instruction can have a source modifier that
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* performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
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* or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
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*/
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if (inst->src[0].negate) {
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inst->opcode = BRW_OPCODE_NOT;
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inst->src[0].negate = false;
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} else {
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inst->opcode = BRW_OPCODE_MOV;
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}
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inst->resize_sources(1);
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progress = true;
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break;
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}
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break;
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case BRW_OPCODE_CMP:
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if ((inst->conditional_mod == BRW_CONDITIONAL_Z ||
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inst->conditional_mod == BRW_CONDITIONAL_NZ) &&
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inst->src[1].is_zero() &&
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(inst->src[0].abs || inst->src[0].negate)) {
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inst->src[0].abs = false;
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inst->src[0].negate = false;
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progress = true;
|
|
break;
|
|
}
|
|
break;
|
|
case BRW_OPCODE_SEL:
|
|
if (inst->src[0].equals(inst->src[1])) {
|
|
inst->opcode = BRW_OPCODE_MOV;
|
|
inst->predicate = BRW_PREDICATE_NONE;
|
|
inst->predicate_inverse = false;
|
|
inst->resize_sources(1);
|
|
progress = true;
|
|
} else if (inst->saturate && inst->src[1].file == IMM) {
|
|
switch (inst->conditional_mod) {
|
|
case BRW_CONDITIONAL_LE:
|
|
case BRW_CONDITIONAL_L:
|
|
switch (inst->src[1].type) {
|
|
case BRW_TYPE_F:
|
|
if (inst->src[1].f >= 1.0f) {
|
|
inst->opcode = BRW_OPCODE_MOV;
|
|
inst->conditional_mod = BRW_CONDITIONAL_NONE;
|
|
inst->resize_sources(1);
|
|
progress = true;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case BRW_CONDITIONAL_GE:
|
|
case BRW_CONDITIONAL_G:
|
|
switch (inst->src[1].type) {
|
|
case BRW_TYPE_F:
|
|
if (inst->src[1].f <= 0.0f) {
|
|
inst->opcode = BRW_OPCODE_MOV;
|
|
inst->conditional_mod = BRW_CONDITIONAL_NONE;
|
|
inst->resize_sources(1);
|
|
progress = true;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case BRW_OPCODE_CSEL:
|
|
if (brw_type_is_float(inst->dst.type)) {
|
|
/* This transformation can both clean up spurious modifiers
|
|
* (making assembly dumps easier to read) and convert GE with -abs
|
|
* to LE with abs. See abs handling below.
|
|
*/
|
|
if (inst->src[2].negate) {
|
|
inst->conditional_mod = brw_swap_cmod(inst->conditional_mod);
|
|
inst->src[2].negate = false;
|
|
progress = true;
|
|
}
|
|
|
|
if (inst->src[2].abs) {
|
|
switch (inst->conditional_mod) {
|
|
case BRW_CONDITIONAL_Z:
|
|
case BRW_CONDITIONAL_NZ:
|
|
inst->src[2].abs = false;
|
|
progress = true;
|
|
break;
|
|
|
|
case BRW_CONDITIONAL_LE:
|
|
/* Converting to Z can help constant propagation into src0
|
|
* and src1.
|
|
*/
|
|
inst->conditional_mod = BRW_CONDITIONAL_Z;
|
|
inst->src[2].abs = false;
|
|
progress = true;
|
|
break;
|
|
|
|
default:
|
|
/* GE or L conditions with absolute value could be used to
|
|
* implement isnan(x) in CSEL. Transforming G with absolute
|
|
* value to NZ is **not** NaN safe.
|
|
*/
|
|
break;
|
|
}
|
|
}
|
|
} else if (brw_type_is_sint(inst->src[2].type)) {
|
|
/* Integer transformations are more challenging than floating
|
|
* point transformations due to INT_MIN == -(INT_MIN) ==
|
|
* abs(INT_MIN).
|
|
*/
|
|
if (inst->src[2].negate && inst->src[2].abs) {
|
|
switch (inst->conditional_mod) {
|
|
case BRW_CONDITIONAL_GE:
|
|
inst->src[2].negate = false;
|
|
inst->src[2].abs = false;
|
|
inst->conditional_mod = BRW_CONDITIONAL_Z;
|
|
progress = true;
|
|
break;
|
|
case BRW_CONDITIONAL_L:
|
|
inst->src[2].negate = false;
|
|
inst->src[2].abs = false;
|
|
inst->conditional_mod = BRW_CONDITIONAL_NZ;
|
|
progress = true;
|
|
break;
|
|
case BRW_CONDITIONAL_G:
|
|
/* This is a contradtion. -abs(x) cannot be > 0. */
|
|
inst->opcode = BRW_OPCODE_MOV;
|
|
inst->src[0] = inst->src[1];
|
|
inst->resize_sources(1);
|
|
progress = true;
|
|
break;
|
|
case BRW_CONDITIONAL_LE:
|
|
/* This is a tautology. -abs(x) must be <= 0. */
|
|
inst->opcode = BRW_OPCODE_MOV;
|
|
inst->resize_sources(1);
|
|
progress = true;
|
|
break;
|
|
case BRW_CONDITIONAL_Z:
|
|
case BRW_CONDITIONAL_NZ:
|
|
inst->src[2].negate = false;
|
|
inst->src[2].abs = false;
|
|
progress = true;
|
|
break;
|
|
default:
|
|
unreachable("Impossible icsel condition.");
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
case BRW_OPCODE_MAD:
|
|
if (inst->src[1].file == IMM &&
|
|
inst->src[2].file == IMM &&
|
|
!brw_type_is_vector_imm(inst->src[1].type) &&
|
|
!brw_type_is_vector_imm(inst->src[2].type)) {
|
|
fold_multiplicands_of_MAD(inst);
|
|
|
|
/* This could result in (x + 0). For floats, we want to leave this
|
|
* as an ADD so that a subnormal x will get flushed to zero.
|
|
*/
|
|
assert(inst->opcode == BRW_OPCODE_ADD);
|
|
progress = true;
|
|
break;
|
|
}
|
|
|
|
if (inst->src[1].is_one()) {
|
|
inst->opcode = BRW_OPCODE_ADD;
|
|
inst->src[1] = inst->src[2];
|
|
inst->resize_sources(2);
|
|
progress = true;
|
|
} else if (inst->src[2].is_one()) {
|
|
inst->opcode = BRW_OPCODE_ADD;
|
|
inst->resize_sources(2);
|
|
progress = true;
|
|
}
|
|
break;
|
|
case SHADER_OPCODE_BROADCAST:
|
|
if (is_uniform(inst->src[0])) {
|
|
inst->opcode = BRW_OPCODE_MOV;
|
|
inst->force_writemask_all = true;
|
|
inst->exec_size = 8 * reg_unit(devinfo);
|
|
assert(inst->size_written == inst->dst.component_size(inst->exec_size));
|
|
inst->resize_sources(1);
|
|
progress = true;
|
|
} else if (inst->src[1].file == IMM) {
|
|
inst->opcode = BRW_OPCODE_MOV;
|
|
/* It's possible that the selected component will be too large and
|
|
* overflow the register. This can happen if someone does a
|
|
* readInvocation() from GLSL or SPIR-V and provides an OOB
|
|
* invocationIndex. If this happens and we some how manage
|
|
* to constant fold it in and get here, then component() may cause
|
|
* us to start reading outside of the VGRF which will lead to an
|
|
* assert later. Instead, just let it wrap around if it goes over
|
|
* exec_size.
|
|
*/
|
|
const unsigned comp = inst->src[1].ud & (inst->exec_size - 1);
|
|
inst->src[0] = component(inst->src[0], comp);
|
|
inst->force_writemask_all = true;
|
|
inst->exec_size = 8 * reg_unit(devinfo);
|
|
assert(inst->size_written == inst->dst.component_size(inst->exec_size));
|
|
inst->resize_sources(1);
|
|
progress = true;
|
|
}
|
|
break;
|
|
|
|
case SHADER_OPCODE_SHUFFLE:
|
|
if (is_uniform(inst->src[0])) {
|
|
inst->opcode = BRW_OPCODE_MOV;
|
|
inst->resize_sources(1);
|
|
progress = true;
|
|
} else if (inst->src[1].file == IMM) {
|
|
inst->opcode = BRW_OPCODE_MOV;
|
|
inst->src[0] = component(inst->src[0],
|
|
inst->src[1].ud);
|
|
inst->resize_sources(1);
|
|
progress = true;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Ensure that the correct source has the immediate value. 2-source
|
|
* instructions must have the immediate in src[1]. On Gfx12 and later,
|
|
* some 3-source instructions can have the immediate in src[0] or
|
|
* src[2]. It's complicated, so don't mess with 3-source instructions
|
|
* here.
|
|
*/
|
|
if (progress && inst->sources == 2 && inst->is_commutative()) {
|
|
if (inst->src[0].file == IMM) {
|
|
brw_reg tmp = inst->src[1];
|
|
inst->src[1] = inst->src[0];
|
|
inst->src[0] = tmp;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (progress)
|
|
s.invalidate_analysis(BRW_DEPENDENCY_INSTRUCTION_DATA_FLOW |
|
|
BRW_DEPENDENCY_INSTRUCTION_DETAIL);
|
|
|
|
return progress;
|
|
}
|