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mesa/src/intel
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Ian Romanick 97e3c6a12a intel/brw: Use range analysis to optimize fsign 
shader-db:

Meteor Lake, DG2, and Tiger Lake had similar results. (Meteor Lake shown)
total instructions in shared programs: 19674784 -> 19665960 (-0.04%)
instructions in affected programs: 933425 -> 924601 (-0.95%)
helped: 3656 / HURT: 0

total cycles in shared programs: 810343919 -> 810241030 (-0.01%)
cycles in affected programs: 56752034 -> 56649145 (-0.18%)
helped: 3032 / HURT: 434

LOST:   11
GAINED: 0

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 20315795 -> 20305856 (-0.05%)
instructions in affected programs: 979698 -> 969759 (-1.01%)
helped: 3845 / HURT: 0

total cycles in shared programs: 830600281 -> 830534694 (<.01%)
cycles in affected programs: 45675615 -> 45610028 (-0.14%)
helped: 3250 / HURT: 325

total spills in shared programs: 4583 -> 4565 (-0.39%)
spills in affected programs: 180 -> 162 (-10.00%)
helped: 3 / HURT: 0

total fills in shared programs: 5245 -> 5219 (-0.50%)
fills in affected programs: 379 -> 353 (-6.86%)
helped: 3 / HURT: 0

LOST:   14
GAINED: 8

fossil-db:

All Intel platforms except Tiger Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 154024263 -> 154023814 (-0.00%)
Cycle count: 17463341602 -> 17461726239 (-0.01%); split: -0.01%, +0.00%

Totals from 322 (0.05% of 631440) affected shaders:
Instrs: 199933 -> 199484 (-0.22%)
Cycle count: 168492537 -> 166877174 (-0.96%); split: -0.96%, +0.00%

Tiger Lake
Instrs: 149984723 -> 149984287 (-0.00%)
Cycle count: 15238596937 -> 15239260415 (+0.00%); split: -0.00%, +0.01%
Max dispatch width: 5553408 -> 5553424 (+0.00%)

Totals from 318 (0.05% of 631414) affected shaders:
Instrs: 179624 -> 179188 (-0.24%)
Cycle count: 160724533 -> 161388011 (+0.41%); split: -0.06%, +0.48%
Max dispatch width: 3296 -> 3312 (+0.49%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
2024-05-14 01:28:21 +00:00
..
blorp intel/blorp: remove unused blorp batch flag 2024-04-10 05:38:24 +00:00
ci ci: uprev CTS to vulkan-cts-1.3.8.0 2024-04-17 21:22:36 +00:00
common intel: move debug identifier out of libintel_dev 2024-05-11 01:52:01 +00:00
compiler intel/brw: Use range analysis to optimize fsign 2024-05-14 01:28:21 +00:00
decoder intel/decoder: Add intel_print_group_custom_spacing() 2024-04-24 17:07:50 +00:00
dev intel/brw: Hide register pressure information in dumps 2024-05-11 02:17:56 +00:00
ds intel/ds: Nuke ralloc_ctx and ralloc_cfg 2024-05-07 21:44:34 +00:00
genxml intel/genxml/xe2: Update definition of INTERFACE_DESCRIPTOR_DATA 2024-04-03 20:21:04 +00:00
isl isl: Set MOCS to uncached for Gfx12.0 blitter sources/destinations 2024-04-25 08:05:48 +00:00
nullhw-layer docs: replace references to the deprecated VK_INSTANCE_LAYERS with the new VK_LOADER_LAYERS_ENABLE 2024-04-02 18:08:52 +00:00
perf intel/perf: Add function to open perf stream 2024-05-07 21:44:34 +00:00
shaders intel: Build float64 shader only for Vulkan 2024-04-26 14:08:32 +00:00
tools intel: move debug identifier out of libintel_dev 2024-05-11 01:52:01 +00:00
vulkan intel: move debug identifier out of libintel_dev 2024-05-11 01:52:01 +00:00
vulkan_hasvk intel: move debug identifier out of libintel_dev 2024-05-11 01:52:01 +00:00
meson.build intel: Only build shaders with anv and iris 2024-02-21 20:53:36 +00:00