mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-21 22:20:14 +01:00
6ce8592836
Vulkan doesn't have a stencilWriteEnable bit like it does for depth. Instead, you have a stencil mask. Since the stencil mask is handled as dynamic state, we have to handle it later during command buffer construction. This, combined with a later commit, seems to help Dota2 on my Broadwell GT3e desktop by a couple percent because it allows the hardware to move the depth and stencil writes to early in more cases. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
433 lines
16 KiB
C
433 lines
16 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#if GEN_GEN == 8
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void
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gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
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{
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uint32_t count = cmd_buffer->state.dynamic.viewport.count;
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const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
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struct anv_state sf_clip_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
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for (uint32_t i = 0; i < count; i++) {
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const VkViewport *vp = &viewports[i];
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/* The gen7 state struct has just the matrix and guardband fields, the
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* gen8 struct adds the min/max viewport fields. */
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struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
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.ViewportMatrixElementm00 = vp->width / 2,
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.ViewportMatrixElementm11 = vp->height / 2,
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.ViewportMatrixElementm22 = 1.0,
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.ViewportMatrixElementm30 = vp->x + vp->width / 2,
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.ViewportMatrixElementm31 = vp->y + vp->height / 2,
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.ViewportMatrixElementm32 = 0.0,
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.XMinClipGuardband = -1.0f,
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.XMaxClipGuardband = 1.0f,
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.YMinClipGuardband = -1.0f,
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.YMaxClipGuardband = 1.0f,
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.XMinViewPort = vp->x,
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.XMaxViewPort = vp->x + vp->width - 1,
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.YMinViewPort = MIN2(vp->y, vp->y + vp->height),
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.YMaxViewPort = MAX2(vp->y, vp->y + vp->height) - 1,
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};
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GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
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&sf_clip_viewport);
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}
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if (!cmd_buffer->device->info.has_llc)
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anv_state_clflush(sf_clip_state);
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anv_batch_emit(&cmd_buffer->batch,
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GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
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clip.SFClipViewportPointer = sf_clip_state.offset;
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}
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}
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void
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gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
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bool depth_clamp_enable)
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{
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uint32_t count = cmd_buffer->state.dynamic.viewport.count;
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const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
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for (uint32_t i = 0; i < count; i++) {
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const VkViewport *vp = &viewports[i];
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struct GENX(CC_VIEWPORT) cc_viewport = {
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.MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f,
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.MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f,
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};
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GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
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}
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if (!cmd_buffer->device->info.has_llc)
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anv_state_clflush(cc_state);
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anv_batch_emit(&cmd_buffer->batch,
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GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
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cc.CCViewportPointer = cc_state.offset;
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}
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}
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#endif
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static void
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__emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
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{
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uint32_t sf_dw[GENX(3DSTATE_SF_length)];
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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.LineWidth = cmd_buffer->state.dynamic.line_width,
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};
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GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
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/* FIXME: gen9.fs */
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
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cmd_buffer->state.pipeline->gen8.sf);
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}
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void
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gen9_emit_sf_state(struct anv_cmd_buffer *cmd_buffer);
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#if GEN_GEN == 9
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void
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gen9_emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
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{
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__emit_genx_sf_state(cmd_buffer);
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}
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#endif
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#if GEN_GEN == 8
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static void
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__emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
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{
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if (cmd_buffer->device->info.is_cherryview)
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gen9_emit_sf_state(cmd_buffer);
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else
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__emit_genx_sf_state(cmd_buffer);
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}
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#else
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static void
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__emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
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{
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__emit_genx_sf_state(cmd_buffer);
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}
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#endif
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void
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genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
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__emit_sf_state(cmd_buffer);
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}
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
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uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
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struct GENX(3DSTATE_RASTER) raster = {
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GENX(3DSTATE_RASTER_header),
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.GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
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.GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
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.GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
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};
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GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
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anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
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pipeline->gen8.raster);
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}
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/* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
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* 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
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* across different state packets for gen8 and gen9. We handle that by
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* using a big old #if switch here.
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*/
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#if GEN_GEN == 8
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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GENX(COLOR_CALC_STATE_length) * 4,
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64);
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struct GENX(COLOR_CALC_STATE) cc = {
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.BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
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.BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
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.BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
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.BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
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.StencilReferenceValue = d->stencil_reference.front & 0xff,
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.BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
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};
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GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
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if (!cmd_buffer->device->info.has_llc)
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anv_state_clflush(cc_state);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
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ccp.ColorCalcStatePointer = cc_state.offset;
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ccp.ColorCalcStatePointerValid = true;
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}
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}
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
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uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
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GENX(3DSTATE_WM_DEPTH_STENCIL_header),
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.StencilTestMask = d->stencil_compare_mask.front & 0xff,
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.StencilWriteMask = d->stencil_write_mask.front & 0xff,
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.BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
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.BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
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.StencilBufferWriteEnable =
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(d->stencil_write_mask.front || d->stencil_write_mask.back) &&
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pipeline->writes_stencil,
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};
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GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
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&wm_depth_stencil);
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anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
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pipeline->gen8.wm_depth_stencil);
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}
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#else
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if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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GEN9_COLOR_CALC_STATE_length * 4,
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64);
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struct GEN9_COLOR_CALC_STATE cc = {
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.BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
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.BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
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.BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
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.BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
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};
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GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
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if (!cmd_buffer->device->info.has_llc)
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anv_state_clflush(cc_state);
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anv_batch_emit(&cmd_buffer->batch, GEN9_3DSTATE_CC_STATE_POINTERS, ccp) {
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ccp.ColorCalcStatePointer = cc_state.offset;
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ccp.ColorCalcStatePointerValid = true;
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}
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}
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
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GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
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.StencilTestMask = d->stencil_compare_mask.front & 0xff,
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.StencilWriteMask = d->stencil_write_mask.front & 0xff,
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.BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
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.BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
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.StencilReferenceValue = d->stencil_reference.front & 0xff,
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.BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
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.StencilBufferWriteEnable =
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(d->stencil_write_mask.front || d->stencil_write_mask.back) &&
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pipeline->writes_stencil,
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};
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GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
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anv_batch_emit_merge(&cmd_buffer->batch, dwords,
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pipeline->gen9.wm_depth_stencil);
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}
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#endif
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER)) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
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vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
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vf.CutIndex = cmd_buffer->state.restart_index;
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}
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}
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cmd_buffer->state.dirty = 0;
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}
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void genX(CmdBindIndexBuffer)(
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VkCommandBuffer commandBuffer,
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VkBuffer _buffer,
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VkDeviceSize offset,
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VkIndexType indexType)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
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static const uint32_t vk_to_gen_index_type[] = {
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[VK_INDEX_TYPE_UINT16] = INDEX_WORD,
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[VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
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};
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static const uint32_t restart_index_for_type[] = {
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[VK_INDEX_TYPE_UINT16] = UINT16_MAX,
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[VK_INDEX_TYPE_UINT32] = UINT32_MAX,
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};
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cmd_buffer->state.restart_index = restart_index_for_type[indexType];
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
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ib.IndexFormat = vk_to_gen_index_type[indexType];
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ib.MemoryObjectControlState = GENX(MOCS);
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ib.BufferStartingAddress =
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(struct anv_address) { buffer->bo, buffer->offset + offset };
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ib.BufferSize = buffer->size - offset;
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}
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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}
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/* Set of stage bits for which are pipelined, i.e. they get queued by the
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* command streamer for later execution.
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*/
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#define ANV_PIPELINE_STAGE_PIPELINED_BITS \
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(VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
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VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
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VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
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VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
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VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
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VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
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VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
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VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
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VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
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VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
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VK_PIPELINE_STAGE_TRANSFER_BIT | \
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VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
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VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
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VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
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void genX(CmdSetEvent)(
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VkCommandBuffer commandBuffer,
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VkEvent _event,
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VkPipelineStageFlags stageMask)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_event, event, _event);
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
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pc.StallAtPixelScoreboard = true;
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pc.CommandStreamerStallEnable = true;
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}
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pc.DestinationAddressType = DAT_PPGTT,
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pc.PostSyncOperation = WriteImmediateData,
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pc.Address = (struct anv_address) {
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&cmd_buffer->device->dynamic_state_block_pool.bo,
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event->state.offset
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};
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pc.ImmediateData = VK_EVENT_SET;
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}
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}
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void genX(CmdResetEvent)(
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VkCommandBuffer commandBuffer,
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VkEvent _event,
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VkPipelineStageFlags stageMask)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_event, event, _event);
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
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if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
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pc.StallAtPixelScoreboard = true;
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pc.CommandStreamerStallEnable = true;
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}
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pc.DestinationAddressType = DAT_PPGTT;
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pc.PostSyncOperation = WriteImmediateData;
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pc.Address = (struct anv_address) {
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&cmd_buffer->device->dynamic_state_block_pool.bo,
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event->state.offset
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};
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pc.ImmediateData = VK_EVENT_RESET;
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}
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}
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void genX(CmdWaitEvents)(
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VkCommandBuffer commandBuffer,
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uint32_t eventCount,
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const VkEvent* pEvents,
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VkPipelineStageFlags srcStageMask,
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VkPipelineStageFlags destStageMask,
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uint32_t memoryBarrierCount,
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const VkMemoryBarrier* pMemoryBarriers,
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uint32_t bufferMemoryBarrierCount,
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const VkBufferMemoryBarrier* pBufferMemoryBarriers,
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uint32_t imageMemoryBarrierCount,
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const VkImageMemoryBarrier* pImageMemoryBarriers)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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for (uint32_t i = 0; i < eventCount; i++) {
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ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
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anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
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sem.WaitMode = PollingMode,
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sem.CompareOperation = COMPARE_SAD_EQUAL_SDD,
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|
sem.SemaphoreDataDword = VK_EVENT_SET,
|
|
sem.SemaphoreAddress = (struct anv_address) {
|
|
&cmd_buffer->device->dynamic_state_block_pool.bo,
|
|
event->state.offset
|
|
};
|
|
}
|
|
}
|
|
|
|
genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
|
|
false, /* byRegion */
|
|
memoryBarrierCount, pMemoryBarriers,
|
|
bufferMemoryBarrierCount, pBufferMemoryBarriers,
|
|
imageMemoryBarrierCount, pImageMemoryBarriers);
|
|
}
|