Konstantin Seurer 658ce711d5 radv/rt: Lower ray payloads to registers ... This should allow for cross stage optimizations and it reduces latency caused by scratch access. Totals from 44 (9.69% of 454) affected shaders: MaxWaves: 432 -> 436 (+0.93%) Instrs: 2740662 -> 1610327 (-41.24%); split: -41.24%, +0.00% CodeSize: 14616932 -> 8573620 (-41.34%) VGPRs: 4880 -> 4816 (-1.31%) SpillSGPRs: 464 -> 294 (-36.64%) Latency: 18548886 -> 11465281 (-38.19%); split: -38.19%, +0.00% InvThroughput: 5195964 -> 3066729 (-40.98%); split: -40.98%, +0.00% VClause: 99672 -> 55611 (-44.21%) SClause: 65827 -> 38697 (-41.21%) Copies: 231231 -> 137676 (-40.46%); split: -40.47%, +0.01% Branches: 111379 -> 65865 (-40.86%); split: -40.87%, +0.00% PreSGPRs: 3854 -> 3812 (-1.09%); split: -1.19%, +0.10% PreVGPRs: 4518 -> 4439 (-1.75%); split: -1.84%, +0.09% Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26431>		2024-01-09 13:02:11 +00:00
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addrlib	amd/common: update addrlib for gfx11.5	2023-10-20 07:32:34 +00:00
ci	radv: stop clearing CMASK to 0xcc when FMASK is present on GFX9	2024-01-03 13:58:06 +00:00
common	Revert "ac/nir: Export clip distances according to clip_cull_mask"	2024-01-09 02:36:19 +00:00
compiler	aco: apply fneg/fabs to VOP3P	2024-01-08 13:26:19 +00:00
drm-shim	amd: Use align64 instead of ALIGN for 64 bit value parameter	2024-01-03 22:02:17 +00:00
llvm	nir: remove sad_u8x4	2024-01-05 18:55:22 +00:00
registers	ac/registers: allow to parse GCVM_L2_PROTECTION_FAULT_STATUS	2023-10-30 08:10:22 +00:00
vpelib	amd,radeonsi: add libvpe	2023-12-01 00:23:38 +00:00
vulkan	radv/rt: Lower ray payloads to registers	2024-01-09 13:02:11 +00:00
meson.build	amd,radeonsi: add libvpe	2023-12-01 00:23:38 +00:00