mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-22 07:00:12 +01:00
6513bf65c3
This is similar in principle to the previous commit "intel/brw/xe3+:
brw_compile_fs() implementation for Xe3+." but applied to compute-like
shader stages. It changes the implementation of brw_compile_cs/task/mesh()
to reduce compile time and take advantage of wider dispatch modes more
aggressively than the original logic, since as of Xe3 SIMD32 builds
succeed without spills in most cases thanks to VRT.
The new "optimistic" SIMD selection logic starts with the SIMD width
that is potentially highest performance and only compiles additional
narrower variants if that fails (typically due to spilling), while the
old "pessimistic" logic did the opposite: It started with the
narrowest SIMD width and compiled additional variants with increasing
register pressure until one of them failed to compile.
In typical non-spilling cases where we formerly compiled SIMD16 and
SIMD32 variants of the same compute shader, this change will halve the
number of backend compilations required to build it.
XXX - Possibly don't do this in cases with variable workgroup size
until effect on runtime performance can be measured directly.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
v2: Don't do this for now in cases with variable workgroup size, still
compile every possible variant in such cases.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32664>
398 lines
13 KiB
C++
398 lines
13 KiB
C++
/*
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* Copyright © 2021 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_private.h"
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#include "compiler/shader_info.h"
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#include "intel/dev/intel_debug.h"
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#include "intel/dev/intel_device_info.h"
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#include "util/ralloc.h"
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#include <gtest/gtest.h>
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enum {
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SIMD8 = 0,
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SIMD16 = 1,
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SIMD32 = 2,
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};
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const bool spilled = true;
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const bool not_spilled = false;
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class SIMDSelectionTest : public ::testing::Test {
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protected:
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SIMDSelectionTest()
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: mem_ctx(ralloc_context(NULL))
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, devinfo(rzalloc(mem_ctx, intel_device_info))
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, prog_data(rzalloc(mem_ctx, struct brw_cs_prog_data))
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, simd_state{
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.devinfo = devinfo,
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.prog_data = prog_data,
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}
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{
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process_intel_debug_variable();
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}
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~SIMDSelectionTest() {
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ralloc_free(mem_ctx);
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};
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void *mem_ctx;
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intel_device_info *devinfo;
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struct brw_cs_prog_data *prog_data;
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brw_simd_selection_state simd_state;
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};
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class SIMDSelectionCS : public SIMDSelectionTest {
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protected:
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SIMDSelectionCS() {
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prog_data->base.stage = MESA_SHADER_COMPUTE;
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prog_data->local_size[0] = 32;
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prog_data->local_size[1] = 1;
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prog_data->local_size[2] = 1;
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devinfo->max_cs_workgroup_threads = 64;
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}
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};
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TEST_F(SIMDSelectionCS, DefaultsToSIMD16)
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{
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), SIMD16);
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}
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TEST_F(SIMDSelectionCS, TooBigFor16)
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{
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prog_data->local_size[0] = devinfo->max_cs_workgroup_threads;
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prog_data->local_size[1] = 32;
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prog_data->local_size[2] = 1;
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, spilled);
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ASSERT_EQ(brw_simd_select(simd_state), SIMD32);
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}
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TEST_F(SIMDSelectionCS, WorkgroupSize1)
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{
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prog_data->local_size[0] = 1;
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prog_data->local_size[1] = 1;
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prog_data->local_size[2] = 1;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
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}
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TEST_F(SIMDSelectionCS, WorkgroupSize8)
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{
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prog_data->local_size[0] = 8;
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prog_data->local_size[1] = 1;
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prog_data->local_size[2] = 1;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
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}
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TEST_F(SIMDSelectionCS, WorkgroupSizeVariable)
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{
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prog_data->local_size[0] = 0;
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prog_data->local_size[1] = 0;
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prog_data->local_size[2] = 0;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
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ASSERT_EQ(prog_data->prog_mask, 1u << SIMD8 | 1u << SIMD16 | 1u << SIMD32);
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const unsigned wg_8_1_1[] = { 8, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8);
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const unsigned wg_16_1_1[] = { 16, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16);
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const unsigned wg_32_1_1[] = { 32, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16);
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}
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TEST_F(SIMDSelectionCS, WorkgroupSizeVariableSpilled)
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{
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prog_data->local_size[0] = 0;
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prog_data->local_size[1] = 0;
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prog_data->local_size[2] = 0;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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brw_simd_mark_compiled(simd_state, SIMD16, spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, spilled);
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ASSERT_EQ(prog_data->prog_mask, 1u << SIMD8 | 1u << SIMD16 | 1u << SIMD32);
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const unsigned wg_8_1_1[] = { 8, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8);
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const unsigned wg_16_1_1[] = { 16, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8);
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const unsigned wg_32_1_1[] = { 32, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8);
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}
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TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8)
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{
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prog_data->local_size[0] = 0;
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prog_data->local_size[1] = 0;
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prog_data->local_size[2] = 0;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
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ASSERT_EQ(prog_data->prog_mask, 1u << SIMD16 | 1u << SIMD32);
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const unsigned wg_8_1_1[] = { 8, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), -1);
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const unsigned wg_16_1_1[] = { 16, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD16);
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const unsigned wg_32_1_1[] = { 32, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD16);
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}
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TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD16)
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{
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prog_data->local_size[0] = 0;
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prog_data->local_size[1] = 0;
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prog_data->local_size[2] = 0;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
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ASSERT_EQ(prog_data->prog_mask, 1u << SIMD8 | 1u << SIMD32);
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const unsigned wg_8_1_1[] = { 8, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), SIMD8);
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const unsigned wg_16_1_1[] = { 16, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), SIMD8);
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const unsigned wg_32_1_1[] = { 32, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD8);
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}
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TEST_F(SIMDSelectionCS, WorkgroupSizeVariableNoSIMD8NoSIMD16)
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{
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prog_data->local_size[0] = 0;
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prog_data->local_size[1] = 0;
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prog_data->local_size[2] = 0;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
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ASSERT_EQ(prog_data->prog_mask, 1u << SIMD32);
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const unsigned wg_8_1_1[] = { 8, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_8_1_1), -1);
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const unsigned wg_16_1_1[] = { 16, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_16_1_1), -1);
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const unsigned wg_32_1_1[] = { 32, 1, 1 };
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ASSERT_EQ(brw_simd_select_for_workgroup_size(devinfo, prog_data, wg_32_1_1), SIMD32);
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}
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TEST_F(SIMDSelectionCS, SpillAtSIMD8)
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{
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, spilled);
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
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}
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TEST_F(SIMDSelectionCS, SpillAtSIMD16)
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{
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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brw_simd_mark_compiled(simd_state, SIMD16, spilled);
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
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}
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TEST_F(SIMDSelectionCS, EnvironmentVariable32)
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{
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intel_debug |= DEBUG_DO32;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
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ASSERT_EQ(brw_simd_select(simd_state), SIMD32);
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}
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TEST_F(SIMDSelectionCS, EnvironmentVariable32ButSpills)
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{
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intel_debug |= DEBUG_DO32;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, spilled);
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ASSERT_EQ(brw_simd_select(simd_state), SIMD16);
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}
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TEST_F(SIMDSelectionCS, Require8)
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{
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simd_state.required_width = 8;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), SIMD8);
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}
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TEST_F(SIMDSelectionCS, Require8ErrorWhenNotCompile)
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{
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simd_state.required_width = 8;
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), -1);
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}
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TEST_F(SIMDSelectionCS, Require16)
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{
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simd_state.required_width = 16;
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), SIMD16);
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}
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TEST_F(SIMDSelectionCS, Require16ErrorWhenNotCompile)
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{
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simd_state.required_width = 16;
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), -1);
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}
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TEST_F(SIMDSelectionCS, Require32)
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{
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simd_state.required_width = 32;
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
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ASSERT_EQ(brw_simd_select(simd_state), SIMD32);
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}
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TEST_F(SIMDSelectionCS, Require32ErrorWhenNotCompile)
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{
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simd_state.required_width = 32;
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_FALSE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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ASSERT_EQ(brw_simd_select(simd_state), -1);
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}
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TEST_F(SIMDSelectionCS, FirstCompiledIsSIMD8)
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{
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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brw_simd_mark_compiled(simd_state, SIMD8, not_spilled);
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ASSERT_TRUE(brw_simd_any_compiled(simd_state));
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ASSERT_EQ(brw_simd_first_compiled(simd_state), SIMD8);
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}
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TEST_F(SIMDSelectionCS, FirstCompiledIsSIMD16)
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{
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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brw_simd_mark_compiled(simd_state, SIMD16, not_spilled);
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ASSERT_TRUE(brw_simd_any_compiled(simd_state));
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ASSERT_EQ(brw_simd_first_compiled(simd_state), SIMD16);
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}
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TEST_F(SIMDSelectionCS, FirstCompiledIsSIMD32)
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{
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD8));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD16));
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ASSERT_TRUE(brw_simd_should_compile(simd_state, SIMD32));
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brw_simd_mark_compiled(simd_state, SIMD32, not_spilled);
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|
|
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ASSERT_TRUE(brw_simd_any_compiled(simd_state));
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ASSERT_EQ(brw_simd_first_compiled(simd_state), SIMD32);
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}
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