mesa/src/intel/compiler
Ian Romanick 65df6122da intel/compiler: Use compare rematerialization pass
Almost all of the spill / fill benefit is in Deus Ex.

Haswell and all Gen8+ platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 17224438 -> 17196395 (-0.16%)
instructions in affected programs: 1518658 -> 1490615 (-1.85%)
helped: 1550
HURT: 3
helped stats (abs) min: 1 max: 170 x̄: 18.11 x̃: 2
helped stats (rel) min: 0.04% max: 8.35% x̄: 1.12% x̃: 0.45%
HURT stats (abs)   min: 5 max: 10 x̄: 6.67 x̃: 5
HURT stats (rel)   min: 0.32% max: 0.41% x̄: 0.35% x̃: 0.32%
95% mean confidence interval for instructions value: -19.86 -16.26
95% mean confidence interval for instructions %-change: -1.19% -1.04%
Instructions are helped.

total cycles in shared programs: 361468455 -> 361288721 (-0.05%)
cycles in affected programs: 197367688 -> 197187954 (-0.09%)
helped: 990
HURT: 683
helped stats (abs) min: 1 max: 119045 x̄: 806.00 x̃: 16
helped stats (rel) min: <.01% max: 38.56% x̄: 1.06% x̃: 0.26%
HURT stats (abs)   min: 1 max: 12190 x̄: 905.14 x̃: 22
HURT stats (rel)   min: <.01% max: 25.18% x̄: 1.16% x̃: 0.47%
95% mean confidence interval for cycles value: -315.45 100.58
95% mean confidence interval for cycles %-change: -0.31% <.01%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 12147 -> 8948 (-26.34%)
spills in affected programs: 5433 -> 2234 (-58.88%)
helped: 343
HURT: 0

total fills in shared programs: 25262 -> 21814 (-13.65%)
fills in affected programs: 7771 -> 4323 (-44.37%)
helped: 343
HURT: 3

LOST:   0
GAINED: 17

Ivy Bridge
total instructions in shared programs: 12083517 -> 12081427 (-0.02%)
instructions in affected programs: 540744 -> 538654 (-0.39%)
helped: 786
HURT: 29
helped stats (abs) min: 1 max: 42 x̄: 2.70 x̃: 2
helped stats (rel) min: 0.06% max: 5.44% x̄: 0.55% x̃: 0.36%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.16% max: 0.95% x̄: 0.38% x̃: 0.31%
95% mean confidence interval for instructions value: -2.83 -2.30
95% mean confidence interval for instructions %-change: -0.57% -0.47%
Instructions are helped.

total cycles in shared programs: 180153463 -> 180124798 (-0.02%)
cycles in affected programs: 72597920 -> 72569255 (-0.04%)
helped: 572
HURT: 249
helped stats (abs) min: 1 max: 14830 x̄: 109.48 x̃: 13
helped stats (rel) min: <.01% max: 8.92% x̄: 0.71% x̃: 0.26%
HURT stats (abs)   min: 1 max: 11060 x̄: 136.37 x̃: 10
HURT stats (rel)   min: <.01% max: 10.85% x̄: 0.54% x̃: 0.32%
95% mean confidence interval for cycles value: -96.22 26.39
95% mean confidence interval for cycles %-change: -0.43% -0.23%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 3625 -> 3623 (-0.06%)
spills in affected programs: 46 -> 44 (-4.35%)
helped: 1
HURT: 0

total fills in shared programs: 4065 -> 4061 (-0.10%)
fills in affected programs: 104 -> 100 (-3.85%)
helped: 1
HURT: 0

LOST:   0
GAINED: 8

Sandy Bridge
total instructions in shared programs: 10879656 -> 10878699 (<.01%)
instructions in affected programs: 275167 -> 274210 (-0.35%)
helped: 544
HURT: 0
helped stats (abs) min: 1 max: 20 x̄: 1.76 x̃: 1
helped stats (rel) min: 0.06% max: 3.11% x̄: 0.39% x̃: 0.25%
95% mean confidence interval for instructions value: -1.97 -1.55
95% mean confidence interval for instructions %-change: -0.43% -0.36%
Instructions are helped.

total cycles in shared programs: 154089096 -> 154081132 (<.01%)
cycles in affected programs: 4422722 -> 4414758 (-0.18%)
helped: 459
HURT: 214
helped stats (abs) min: 1 max: 258 x̄: 26.67 x̃: 8
helped stats (rel) min: <.01% max: 5.45% x̄: 0.51% x̃: 0.14%
HURT stats (abs)   min: 1 max: 226 x̄: 19.99 x̃: 4
HURT stats (rel)   min: <.01% max: 3.15% x̄: 0.34% x̃: 0.09%
95% mean confidence interval for cycles value: -15.51 -8.15
95% mean confidence interval for cycles %-change: -0.31% -0.17%
Cycles are helped.

total spills in shared programs: 2880 -> 2876 (-0.14%)
spills in affected programs: 636 -> 632 (-0.63%)
helped: 2
HURT: 0

total fills in shared programs: 3161 -> 3157 (-0.13%)
fills in affected programs: 1519 -> 1515 (-0.26%)
helped: 2
HURT: 0

LOST:   0
GAINED: 2

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8157361 -> 8155067 (-0.03%)
instructions in affected programs: 382491 -> 380197 (-0.60%)
helped: 677
HURT: 0
helped stats (abs) min: 1 max: 43 x̄: 3.39 x̃: 2
helped stats (rel) min: 0.09% max: 5.19% x̄: 0.66% x̃: 0.42%
95% mean confidence interval for instructions value: -3.76 -3.01
95% mean confidence interval for instructions %-change: -0.72% -0.59%
Instructions are helped.

total cycles in shared programs: 188588292 -> 188583040 (<.01%)
cycles in affected programs: 3155064 -> 3149812 (-0.17%)
helped: 377
HURT: 13
helped stats (abs) min: 2 max: 180 x̄: 14.13 x̃: 6
helped stats (rel) min: <.01% max: 3.96% x̄: 0.39% x̃: 0.12%
HURT stats (abs)   min: 2 max: 8 x̄: 5.85 x̃: 6
HURT stats (rel)   min: <.01% max: 0.22% x̄: 0.06% x̃: 0.04%
95% mean confidence interval for cycles value: -15.67 -11.27
95% mean confidence interval for cycles %-change: -0.45% -0.30%
Cycles are helped.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-05-31 08:47:03 -07:00
..
brw_cfg.cpp intel/cfg: Represent divergent control flow paths caused by non-uniform loop execution. 2017-12-07 18:27:05 -08:00
brw_cfg.h
brw_clip.h
brw_clip_line.c
brw_clip_point.c
brw_clip_tri.c i965: Don't emit MOVs with undefined registers for Gen4 point clipping. 2018-02-28 15:03:51 -08:00
brw_clip_unfilled.c
brw_clip_util.c
brw_compile_clip.c intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_compile_sf.c intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_compiler.c iris: Ask st to vectorize our IO. 2019-05-28 01:06:48 -07:00
brw_compiler.h intel: Move brw_prog_key_set_id from i965 to the compiler. 2019-05-21 15:05:38 -07:00
brw_dead_control_flow.cpp
brw_dead_control_flow.h
brw_debug_recompile.c i965: Move program key debugging to the compiler. 2019-04-16 09:01:15 -07:00
brw_disasm.c intel/disasm: Disassemble immediate value properly for dim 2019-05-07 14:33:48 -07:00
brw_disasm_info.c intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_disasm_info.h i965: Stop including brw_cfg.h in brw_disasm_info.h 2017-11-17 21:51:16 -08:00
brw_eu.c intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_eu.h intel/fs: Do a stalling MFENCE in endInvocationInterlock() 2019-05-30 14:00:26 +00:00
brw_eu_compact.c intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits 2019-04-18 11:05:18 +02:00
brw_eu_defines.h intel/fs: Add support for bindless image load/store/atomic 2019-04-19 19:56:42 +00:00
brw_eu_emit.c intel/fs: Do a stalling MFENCE in endInvocationInterlock() 2019-05-30 14:00:26 +00:00
brw_eu_util.c
brw_eu_validate.c intel/compiler: validate region restrictions for mixed float mode 2019-04-18 13:22:46 +02:00
brw_fs.cpp intel/compiler: Implement TCS 8_PATCH mode and INTEL_DEBUG=tcs8 2019-05-14 13:16:30 -07:00
brw_fs.h intel/compiler: Implement TCS 8_PATCH mode and INTEL_DEBUG=tcs8 2019-05-14 13:16:30 -07:00
brw_fs_bank_conflicts.cpp i965/fs: unspills shoudn't use grf127 as dest since Gen8+ 2018-07-12 18:02:26 +02:00
brw_fs_builder.h intel/compiler: Improve fix_3src_operand() 2019-04-22 16:54:31 -07:00
brw_fs_cmod_propagation.cpp intel/fs: Allow cmod propagation to instructions with saturate modifier 2019-05-14 11:38:21 -07:00
brw_fs_combine_constants.cpp intel/fs: Fix D to W conversion in opt_combine_constants 2019-04-23 19:48:33 -07:00
brw_fs_copy_propagation.cpp intel/fs/copy-prop: Don't walk all the ACPs for each instruction 2019-05-10 09:10:17 -05:00
brw_fs_cse.cpp Revert "intel/compiler: split is_partial_write() into two variants" 2019-04-25 09:19:10 +02:00
brw_fs_dead_code_eliminate.cpp Revert "intel/compiler: split is_partial_write() into two variants" 2019-04-25 09:19:10 +02:00
brw_fs_generator.cpp intel/fs: Do a stalling MFENCE in endInvocationInterlock() 2019-05-30 14:00:26 +00:00
brw_fs_live_variables.cpp intel/fs/live_variables: Do compute_start_end in BITSET_WORD chunks 2019-05-16 02:14:40 +00:00
brw_fs_live_variables.h intel/fs: Restrict live intervals to the subset possibly reachable from any definition. 2017-12-07 18:27:04 -08:00
brw_fs_lower_pack.cpp
brw_fs_lower_regioning.cpp intel/compiler: workaround for SIMD8 half-float MAD in gen8 2019-04-18 11:05:18 +02:00
brw_fs_nir.cpp intel/fs: Do a stalling MFENCE in endInvocationInterlock() 2019-05-30 14:00:26 +00:00
brw_fs_reg_allocate.cpp intel/fs/ra: Choose a spill reg before throwing away the graph 2019-05-16 02:13:09 +00:00
brw_fs_register_coalesce.cpp Revert "intel/compiler: split is_partial_write() into two variants" 2019-04-25 09:19:10 +02:00
brw_fs_saturate_propagation.cpp Revert "intel/compiler: split is_partial_write() into two variants" 2019-04-25 09:19:10 +02:00
brw_fs_sel_peephole.cpp Revert "intel/compiler: split is_partial_write() into two variants" 2019-04-25 09:19:10 +02:00
brw_fs_validate.cpp intel: disable FS IR validation in release mode. 2018-10-15 18:10:27 -07:00
brw_fs_visitor.cpp intel/compiler/fs/icl: Use dummy masked urb write for tess eval 2019-04-25 22:00:43 +03:00
brw_inst.h intel/compiler: add instruction setters for Src1Type and Src2Type. 2019-04-18 11:05:18 +02:00
brw_interpolation_map.c intel/compiler: Silence unused parameter warning in brw_interpolation_map.c 2019-03-06 08:35:36 -08:00
brw_ir_allocator.h intel/ir: Don't allow allocating zero registers 2018-12-11 21:26:23 -06:00
brw_ir_fs.h Revert "intel/compiler: split is_partial_write() into two variants" 2019-04-25 09:19:10 +02:00
brw_ir_vec4.h intel: Don't propagate conditional modifiers if a UD source is negated 2018-10-10 13:13:12 -05:00
brw_nir.c intel/compiler: Use compare rematerialization pass 2019-05-31 08:47:03 -07:00
brw_nir.h anv: Use bindless handles for images 2019-04-19 19:56:42 +00:00
brw_nir_analyze_boolean_resolves.c nir: Drop imov/fmov in favor of one mov instruction 2019-05-24 08:38:11 -05:00
brw_nir_analyze_ubo_ranges.c intel/analyze_ubo_ranges: Use nir_src_is_const and friends 2018-11-08 10:09:25 -06:00
brw_nir_attribute_workarounds.c nir/builder: Remove the use_fmov parameter from nir_swizzle 2019-05-24 08:38:11 -05:00
brw_nir_lower_conversions.c intel/compiler: add a NIR pass to lower conversions 2019-04-18 11:05:18 +02:00
brw_nir_lower_cs_intrinsics.c intel/fs: Don't loop when lowering CS intrinsics 2019-04-08 19:29:33 -07:00
brw_nir_lower_image_load_store.c nir/builder: Add a nir_imm_zero helper 2019-04-14 22:25:56 +02:00
brw_nir_lower_mem_access_bit_sizes.c nir/builder: Remove the use_fmov parameter from nir_swizzle 2019-05-24 08:38:11 -05:00
brw_nir_opt_peephole_ffma.c nir: Drop imov/fmov in favor of one mov instruction 2019-05-24 08:38:11 -05:00
brw_nir_tcs_workarounds.c util: use C99 declaration in the for-loop set_foreach() macro 2018-10-25 12:43:18 +01:00
brw_nir_trig_workarounds.py python: Use the print function 2018-07-06 10:04:22 -07:00
brw_packed_float.c
brw_predicated_break.cpp
brw_reg.h intel/compiler: Expand size of the 'nr' field 2019-01-09 16:42:41 -08:00
brw_reg_type.c intel/compiler: add new half-float register type for 3-src instructions 2019-04-18 11:05:18 +02:00
brw_reg_type.h intel/compiler: add a brw_reg_type_is_integer helper 2019-04-18 11:05:18 +02:00
brw_schedule_instructions.cpp intel/compiler: Re-prefix non-logical surface opcodes with VEC4 2019-02-28 16:58:20 -06:00
brw_shader.cpp anv: Implement VK_KHR_shader_atomic_int64 2019-04-19 19:56:42 +00:00
brw_shader.h intel/nir: Take a nir_tex_instr and src index in brw_texture_offset 2019-04-14 22:25:56 +02:00
brw_vec4.cpp intel/compiler: Do not reswizzle dst if instruction writes to flag register 2019-04-16 09:42:08 +00:00
brw_vec4.h intel/compiler: Prevent warnings in the following patch 2019-01-09 16:42:41 -08:00
brw_vec4_builder.h intel/compiler: Lower flrp32 on Gen11+ 2018-02-28 11:15:47 -08:00
brw_vec4_cmod_propagation.cpp intel/compiler: use correct swizzle for replacement 2019-02-27 20:06:42 +00:00
brw_vec4_copy_propagation.cpp intel/compiler: Re-prefix non-logical surface opcodes with VEC4 2019-02-28 16:58:20 -06:00
brw_vec4_cse.cpp i965/vec4: Allow CSE on subset VF constant loads 2018-03-08 15:26:26 -08:00
brw_vec4_dead_code_eliminate.cpp i965/vec4/dce: Don't narrow the write mask if the flags are used 2018-12-17 13:47:06 -08:00
brw_vec4_generator.cpp intel/fs: Do a stalling MFENCE in endInvocationInterlock() 2019-05-30 14:00:26 +00:00
brw_vec4_gs_nir.cpp intel/vec4: Use the new nir_src_is_const and friends 2018-11-08 10:09:25 -06:00
brw_vec4_gs_visitor.cpp intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_vec4_gs_visitor.h
brw_vec4_live_variables.cpp
brw_vec4_live_variables.h
brw_vec4_nir.cpp intel/fs,vec4: Use g0 as the header for MFENCE 2019-05-30 14:00:26 +00:00
brw_vec4_reg_allocate.cpp intel/compiler: Prevent warnings in the following patch 2019-01-09 16:42:41 -08:00
brw_vec4_surface_builder.cpp intel/compiler: Re-prefix non-logical surface opcodes with VEC4 2019-02-28 16:58:20 -06:00
brw_vec4_surface_builder.h intel/vec4: Drop dead code for handling typed surface messages 2019-02-28 16:58:20 -06:00
brw_vec4_tcs.cpp intel/compiler: Implement TCS 8_PATCH mode and INTEL_DEBUG=tcs8 2019-05-14 13:16:30 -07:00
brw_vec4_tcs.h
brw_vec4_tes.cpp intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_vec4_tes.h
brw_vec4_visitor.cpp intel/compiler: fix uninit non-static variable. (v2) 2019-04-25 06:06:57 +10:00
brw_vec4_vs.h i965: Drop support for the legacy SNORM -> Float equation. 2018-01-02 16:51:42 -08:00
brw_vec4_vs_visitor.cpp intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_vue_map.c intel/common: move gen_debug to intel/dev 2019-04-10 13:15:33 -07:00
brw_wm_iz.cpp intel/fs: Extend thread payload layout to SIMD32 2018-06-28 13:19:38 -07:00
gen6_gs_visitor.cpp intel/compiler: Prevent warnings in the following patch 2019-01-09 16:42:41 -08:00
gen6_gs_visitor.h
meson.build intel/compiler: add a NIR pass to lower conversions 2019-04-18 11:05:18 +02:00
test_eu_compact.cpp intel/ir: Fix invalid type aliasing with undefined behavior in test_eu_compact. 2018-02-27 11:42:39 -08:00
test_eu_validate.cpp intel/compiler: validate region restrictions for mixed float mode 2019-04-18 13:22:46 +02:00
test_fs_cmod_propagation.cpp intel/fs: Allow cmod propagation to instructions with saturate modifier 2019-05-14 11:38:21 -07:00
test_fs_copy_propagation.cpp
test_fs_saturate_propagation.cpp intel/compiler: Add unit tests for sat prop for different exec sizes 2019-04-22 16:54:21 -07:00
test_vec4_cmod_propagation.cpp i965/vec4: Silence unused parameter warnings in vec4 compiler tests 2018-12-17 13:47:06 -08:00
test_vec4_copy_propagation.cpp i965/vec4: Silence unused parameter warnings in vec4 compiler tests 2018-12-17 13:47:06 -08:00
test_vec4_dead_code_eliminate.cpp i965/vec4/dce: Don't narrow the write mask if the flags are used 2018-12-17 13:47:06 -08:00
test_vec4_register_coalesce.cpp i965/vec4: Silence unused parameter warnings in vec4 compiler tests 2018-12-17 13:47:06 -08:00
test_vf_float_conversions.cpp