Sagar Ghuge 8166c1f8c1 intel/genxml: Drop incorrect compute aux-inv register entry ... Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958>		2023-07-07 18:05:47 +00:00
..
blorp	intel: use imm-helpers	2023-06-29 07:08:19 +00:00
ci	ci/anv: Add testing of the GLES CTS using ANGLE on TGL.	2023-07-06 23:12:30 +00:00
common	genxml: enable decoding on compute engine	2023-06-27 19:59:06 +00:00
compiler	clc: rework optional subgroup feature	2023-07-07 12:27:35 +00:00
dev	intel/devinfo/i915: Set has_set_pat_uapi for MTL+	2023-06-27 22:06:19 +00:00
ds	intel/ds: Track CCS cache flush bit	2023-06-26 16:08:20 -07:00
genxml	intel/genxml: Drop incorrect compute aux-inv register entry	2023-07-07 18:05:47 +00:00
isl	intel/isl: tile 64 calculations work with 1D surfaces	2023-06-29 23:30:05 +00:00
nullhw-layer	vulkan/layers: Use PUBLIC instead of VK_LAYER_EXPORT	2023-02-17 03:42:34 +00:00
perf	util: reinstate ENUM_PACKED	2023-06-21 21:51:59 +00:00
tools	intel/aubinator_error_decode: add ccs support	2023-06-27 19:59:06 +00:00
vulkan	anv: Use correct CCS0 aux-map register offset in pipe flush	2023-07-07 18:05:47 +00:00
vulkan_hasvk	intel/vulkan: Convert to use nir_foreach_function_impl when possible	2023-07-07 14:02:40 +00:00
meson.build	blorp: add dependency on idep_intel_dev	2023-03-03 13:04:23 +00:00